This paper describes a behavioural asynchronous synthesis system that takes as input an algorithmic description of a design and produces an asynchronous structural implementation. Several example systems are synthesized both synchronously and asynchronously (with no modification to the high level description). In keeping with the well-established observation that asynchronous systems operate at average case time complexity rather than worse case, the asynchronous structures usually operate some 30% faster than their synchronous counterparts, although interesting counterexamples are observed.

Key to the operation of a synchronous system is the (automatically generated) control graph, which is effectively a complex sequence generator controlling the passage of data through the system in time to some synchronising clock. The maximum clock speed is dictated by the slowest time slot. Timeslots containing quicker (less) logic will effectively waste time: the output of the combinational logic in the state will have settled long before the registers reading the data are enabled. If we allow the state to change as soon as the data is ready, by introducing the concepts of 'ready' and 'acknowledge', the control graph becomes a disjoint set of single state machines - it effectively disappears, with the consequence that the timeslot-timeslot transitions become self-controlling. Having removed the necessity for the timeslots to be of equal duration the system becomes self-timing: asynchronous.

Behavioural synthesis can be applied to the design of many different types of circuits. This paper includes results for the synthesis of general control and data path intensive circuits as well as the DES cryptography block, which is of particular interest to those designing secure embedded products.