High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells
Apr. 19, 2004 to Apr. 23, 2004
Marcos Ferretti , University of Southern California
Recep O. Ozdag , University of Southern California
Peter A. Beerel , University of Southern California
This paper presents a back-end design flow for high performance asynchronous ASICs using single-track full-buffer (STFB) standard cells and industry standard CAD tools to perform schematic capture, simulation, layout, placement and routing. This flow is demonstrated and evaluated on a 64-bit asynchronous prefix adder and its test circuitry. The STFB standard cells provide low latency and fast cycle-times at the expense of some timing assumptions. This paper demonstrates that, by controlling top-block sizes and/or wire length within the place & route flow, ultra-high-performance circuits can be automatically designed. In particular, in the TSMC 0.25 ?m process our post-layout STFB standard-cell 64-bit asynchronous prefix adder requires 0.96 mm<sup>2</sup>, offers a latency of 2.1 ns, has a throughput of 1.4 GHz, and operates at five process corners as well as a wide-range of temperatures and voltages.
Marcos Ferretti, Recep O. Ozdag, Peter A. Beerel, "High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells", ASYNC, 2004, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems 2004, pp. 95-105, doi:10.1109/ASYNC.2004.1299291