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| W. J. Bainbridge, W. B. Toms, D. A. Edwards, S. B. Furber, "Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes," 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, pp. 132, Ninth IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'03), 2003. | |||
| BibTex | x | ||
| @article{ 10.1109/ASYNC.2003.1199173, author = {W. J. Bainbridge and W. B. Toms and D. A. Edwards and S. B. Furber}, title = {Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes}, journal ={2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems}, volume = {0}, year = {2003}, issn = {1522-8681}, pages = {132}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASYNC.2003.1199173}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems TI - Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes SN - 1522-8681 SP EP A1 - W. J. Bainbridge, A1 - W. B. Toms, A1 - D. A. Edwards, A1 - S. B. Furber, PY - 2003 KW - null VL - 0 JA - 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems ER - | |||
m-of-n codes can be used for carrying data over self-timed on-chip interconnect links. Such codes can be chosen to have low redundancy, but the costs of encoding/decoding data is high. The key to enabling the cost-effective use of m-of-n codes is to find a suitable mapping of the binary data to the code.
This paper presents a new method for selecting suitable mappings through the decomposition of the complex m-of-n code into an incomplete m-of-n code constructed from groups of smaller, simpler m-of-n and 1-of-n codes.
The circuits used both for completion detection and for encoding/decoding such incomplete codes show reduced logic size and delay compared to their full m-of-n counter-parts. The improvements mean that the incomplete m-of-n codes become attractive for use in on-chip interconnects and network-on-chip designs.