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Ninth IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'03)
Fourteen Ways to Fool Your Synchronizer
Vancouver, B.C., Canada
May 12-May 15
ISBN: 0-7695-1898-2
Ran Ginosar, Israel Institute of Technology
Transferring data between mutually asynchronous clock domains requires safe synchronization. However, the exact nature of synchronization sometimes eludes designers, and as a result synchronization circuits get "optimized" to the point where they do no longer operate correctly. This paper reviews a number of such cases, analyzes the causes of the errors, and offers a correct synchronizer circuit for each case. A correct two-flop synchronizer is presented. After discussing cases that avoid synchronization, the following synchronizers are reviewed: one flop, sneaky path, greedy path, wrong protocol, global reset, async clear, DFT leakage, pulse, slow-to-fast, metastability blocker, parallel and shared flop synchronizers.
Citation:
Ran Ginosar, "Fourteen Ways to Fool Your Synchronizer," async, pp.89, Ninth IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'03), 2003
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