CSDL - Proceedings A

Symposium Committee (PDF)

pp. ix

Steering Committee (PDF)

pp. x

Technical Programme Committee (PDF)

pp. xi

Paper Session 1: High-Speed and Energy-Efficient Pipelines - Chair: Jim Garside

Synchronous Interlocked Pipelines (Abstract)

Hans M. Jacobson, IBM T.J. Watson Research Center

Prabhakar N. Kudva, IBM T.J. Watson Research Center

Pradip Bose, IBM T.J. Watson Research Center

Peter W. Cook, IBM T.J. Watson Research Center

Stanley E. Schuster, IBM T.J. Watson Research Center

pp. 3

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High-Speed QDI Asynchronous Pipelines (Abstract)

Peter A. Beerel, University of Southern California

Recep O. Ozdag, University of Southern California

pp. 13

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Energy-Efficient Pipelines (Abstract)

John Teifel, Cornell University

Clint Kelly, Cornell University

David Fang, Cornell University

Rajit Manohar, Cornell University

David Biermann, Cornell University

pp. 23

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Paper Session 2: Novel Self-Timed Circuit Experiments - Chair: Ivan Sutherland

A Negative-Overhead, Self-Timed Pipeline (Abstract)

Mark R. Greenstreet, University of British Columbia

Brian D. Winters, University of British Columbia

pp. 37

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An Event Spacing Experiment (Abstract)

Aurelien Garivier, L'Ecole Normale Superieure

Anthony Winstanley, University of British Columbia

Mark Greenstreet, University of British Columbia

pp. 47

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Keynote Session I - Chair: Steve Furber

How the ARM Architecture Moved from a Start-Up Idea in Acorn Computers to Become a Global Standard

Paper Session 3: Mixed Synchronous/Asynchronous Communication and Design

Clock Synchronization through Handshake Signalling (Abstract)

Joep Kessels, Philips Research

Suk-Jin Kim, Kwang-Ju Institute of Science and Technology

Ad Peeters, Philips Research

Paul Wielage, Philips Research

pp. 59

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Point to Point GALS Interconnect (Abstract)

Robert Mullins, University of Cambridge

Peter Robinson, University of Cambridge

Simon Moore, University of Cambridge

George Taylor, University of Cambridge

pp. 69

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A Dual-Mode Synchronous/Asynchronous CORDIC Processor (Abstract)

Eckhard Grass, IHP

Koushik Maharatna, IHP

Bodhisatya Sarker, IHP

pp. 76

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An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz (Abstract)

Steven M. Nowick, Columbia University

Montek Singh, University of North Carolina at Chapel Hill

Sergey Rylov, IBM Thomas J. Watson Research Center

Alexander Rylyakov, IBM Thomas J. Watson Research Center

Jose A. Tierno, IBM Thomas J. Watson Research Center

pp. 84

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Keynote Session II - Chair: Peter Robinson

Nanomagnetic Logic Devices

Paper Session 4: Timing Analysis and Verification - Chair: Mark Josephs

Probabilistic Timing Analysis of Asynchronous Systems with Moments of Delays (Abstract)

Rohan Angrish, Stanford University

Supratik Chakraborty, Indian Institute of Technology, Bombay

pp. 99

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Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits (Abstract)

Metehan Özcan, University of Tokyo

Takashi Nanya, University of Tokyo

Masashi Imai, University of Tokyo

pp. 109

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Relative Timing Based Verification of Timed Circuits and Systems (Abstract)

Ken Stevens, Intel Corporation

Peter A. Beerel, University of Southern California

Hoshik Kim, University of Southern California

pp. 115

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Paper Session 5: High-Level Design and Analysis of Self-Timed Circuits - Luciano Lavagno

Asynchronous Circuit Synthesis by Direct Mapping: Interfacing to Environment

Design and Performance Analysis of Buffers: A Constructive Approach

Checking Delay-Insensitivity: 10⁴ Gates and Beyond

Keynote Session III

Mobile Applications

Paper Session 6: Production Testing - Chair: Marly Roncken

Adding Synchronous and LSSD Modes to Asynchronous Circuits (Abstract)

Ad Peeters, Philips Research Laboratories

Frank de Beest, University of Twente

Kees van Berkel, Philips Research Laboratories and Eindhoven University of Technology

pp. 161

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Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach (Abstract)

Alex Kondratyev, Cadence Berkeley Laboratory

Amy Streich, Theseus Logic, Inc.

Lief Sorensen, Theseus Logic, Inc.

pp. 171

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A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems (Abstract)

S. Oetiker, Swiss Federal Institute for Technology

H. Kaeslin, Swiss Federal Institute for Technology

T. Villiger, Swiss Federal Institute for Technology

W. Fichtner, Swiss Federal Institute for Technology

N. Felber, Swiss Federal Institute for Technology

F. Gürkaynak, Swiss Federal Institute for Technology

pp. 181

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On-Chip Structures for Timing Measurements and Test (Abstract)

D. J. Kinniment, Newcastle University

G. Russell, Newcastle University

A. Bystrov, Newcastle University

O. V. Maevsky, Newcastle University

A. V. Yakovlev, Newcastle University

pp. 190

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Paper Session 7: Security - Chair: Joep Kessels

SPA — A Synthesisable Amulet Core for Smartcard pplications

Improving Smart Card Security Using Self-Timed Circuits (Abstract)

George Taylor, University of Cambridge

Simon Moore, University of Cambridge

Ross Anderson, University of Cambridge

Robert Mullins, University of Cambridge

Paul Cunningham, University of Cambridge

pp. 211

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Keynote Session IV - Chair: Peter Beerel

Taking Asynchronous Design to the Market

Author Index (PDF)

pp. 219