We describe an efficient timing analysis technique for extended burst-mode circuits implemented according to the 3D design style. Gate-level 3D circuits with uncertain component delays are analyzed, and safe bounds on timing constraints for correct circuit operation are computed. We employ two passes of multi-valued logic simulation to precisely identify gates where timing constraint violations manifest themselves. Signal propagation delay bounds from the primary inputs to these gates are then used to compute global timing constraints for correct circuit operation. Timing constraints identified by our tool represent conservative approximations to the true timing requirements in the worst-case. In practice, our results are accurate for all of the 3D benchmarks we have experimented with.