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Eindhoven, THE NETHERLANDS
Apr. 7, 1997 to Apr. 10, 1997
ISBN: 0-8186-7922-0
pp: 42
Priyadarsan Patra , Intel Corporation
Stanislav Polonsky , SUNY Stony Brook
Donald S. Fussell , The University of Texas at Austin
ABSTRACT
Asychronous designs have been touted as having potential advantages in average performance, power consumption, modularity, and tolerance of metastability as compared to traditional synchronous logic. While delay-insensitive (DI) asynchronous circuits are theoretically the most desirable type of asynchronous logic because they make the weakest timing assumptions, the complexity of implementing DI circuits in CMOS or similar technologies may make them impractical to use.The fact that event-based DI circuits are ill matched to CMOS does not necessarily mean that they are inherently inefficient, however. In this paper, we show that using Rapid Single Flux Quantum (RSFQ) superconducting circuits, in which information is represented as discrete voltage pulses or magnetic flux quanta, many powerful DI circuit primitives can be implemented at least as efficiently as Boolean logic gates. Since DI logic also alleviates the severe clock skew problems that can be expected at the switching speeds approaching a terahertz in this technology, it may well be a more practical basis for digital circuit design than alternatives traditionally used for CMOS.
CITATION
Priyadarsan Patra, Stanislav Polonsky, Donald S. Fussell, "Delay Insensitive Logic for RSFQ Superconductor Technology", ASYNC, 1997, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems 1997, pp. 42, doi:10.1109/ASYNC.1997.587144
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