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Second International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96)
Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems
Aizu-Wakamatsu, Fukushima, JAPAN
March 18-March 21
ISBN: 0-8186-7298-6
R. Kol, Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
R. Ginosar, Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
G. Samuel, Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
We apply a novel methodology, based on statecharts, for the design of large scale asynchronous systems. The EXV CAD tool offers specification at multiple levels, simulation, animation, and compilation into synthesizable VHDL code. EXV has some verification capabilities, and we add a validation sub-system EXV is originally synchronous, but we discuss how to employ it for asynchronous design. The tool is demonstrated through a simple FSM.
Index Terms:
asynchronous circuits; logic CAD; statecharts; EXV CAD tool; specification; asynchronous design; FSM; large scale asynchronous systems
Citation:
R. Kol, R. Ginosar, G. Samuel, "Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems," async, pp.164, Second International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996
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