CSDL - Proceedings A

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A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield (Abstract)

Bao Liu, CSE Department, UC San Diego, La Jolla, CA 92093-0114. Tel: 858-534-7890, Fax: 858-534-7029, e-mail:

Andrew B. Kahng, CSE Department, UC San Diego, La Jolla, CA 92093-0114. Tel: 858-534-7890, Fax: 858-534-7029, e-mail:

Xu Xu, CSE Department, UC San Diego, La Jolla, CA 92093-0114. Tel: 858-534-7890, Fax: 858-534-7029, e-mail:

Jiang Hu, ECE Department, Texas A&M University, College Station, TX 77843-3182. Tel: 979-847-8768, Fax: 979-84

Ganesh Venkataraman, ECE Department, Texas A&M University, College Station, TX 77843-3182. Tel: 979-847-8768, Fax: 979-84

pp. 24-31

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Control-Flow Aware Communication and Conflict Analysis of Parallel Processes (Abstract)

Axel Siebenborn, FZI Forschungszentrum Informatik, Haid-und-Neu-Str. 10-14, 76131 Karlsruhe, Germany. siebenbo@fzi.de

Alexander Viehl, FZI Forschungszentrum Informatik, Haid-und-Neu-Str. 10-14, 76131 Karlsruhe, Germany. viehl@fzi.de

Oliver Bringmann, FZI Forschungszentrum Informatik, Haid-und-Neu-Str. 10-14, 76131 Karlsruhe, Germany. bringman@fzi.de

Wolfgang Rosenstiel, FZI Forschungszentrum Informatik, Haid-und-Neu-Str. 10-14, 76131 Karlsruhe, Germany; Universit?t T?

pp. 32-37

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Creating Explicit Communication in SoC Models Using Interactive Re-Coding (Abstract)

Pramod Chandraiah, Center for Embedded Computer Systems, University of California, Irvine, California, USA. pramodc@cec

Junyu Peng, Center for Embedded Computer Systems, University of California, Irvine, California, USA. pengj@cecs.

Rainer Domer, Center for Embedded Computer Systems, University of California, Irvine, California, USA. doemer@cecs

pp. 50-55

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A New Boundary Element Method for Multiple-Frequency Parameter Extraction of Lossy Substrates (Abstract)

Xiren Wang, Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China

Wenjian Yu, Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China. Tel: 86-1

Zeyi Wang, Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China

pp. 62-67

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A Programmable Fully-Integrated GPS receiver in 0.18?m CMOS with Test Circuits (Abstract)

Mahta Jenabi, RF IC designer, Unistar Micro Technology Inc, Richmond Hill, ON L4C 0K1. Tel: +1-905-780-1347, Fax:

Noushin Riahi, RF IC designer, Unistar Micro Technology Inc, Richmond Hill, ON L4C 0K1. Tel: +1-905-780-1347, Fax:

Ali Fotowat-Ahmady, RF IC designer, Unistar Micro Technology Inc, Richmond Hill, ON L4C 0K1. Tel: +1-905-780-1347, Fax:

pp. 80-85

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Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches (Abstract)

S. Bhunia, Dept. of Electr. Eng.&Comput. Sci., Case Western Reserve Univ., Cleveland, OH

M. Tabib-Azar, Dept. of Electr. Eng.&Comput. Sci., Case Western Reserve Univ., Cleveland, OH

D. Saab, Dept. of Electr. Eng.&Comput. Sci., Case Western Reserve Univ., Cleveland, OH

pp. 86-91

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22-29GHz Ultra-Wideband CMOS Pulse Generator for Collision Avoidance Short Range Vehicular Radar Sensors (Abstract)

Ahmet Oncu, School of Frontier Sciences, The University of Tokyo, Kashiwa, Japan

B.B.M. Wasanthamala Badalawa, School of Frontier Sciences, The University of Tokyo, Kashiwa, Japan

Tong Wang, School of Frontier Sciences, The University of Tokyo, Kashiwa, Japan

Minoru Fujishima, School of Frontier Sciences, The University of Tokyo, Kashiwa, Japan. fujishima@axcel.k.u-tokyo.ac.j

pp. 94-95

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A Wideband CMOS LC-VCO Using Variable Inductor (Abstract)

K. Ohashi, Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama

Y. Ito, Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama

Y. Yoshihara, Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama

K. Okada, Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama

K. Masu, Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama

pp. 98-99

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Design of Active Substrate Noise Canceller using Power Supply di/dt Detector (Abstract)

Taisuke Kazama, Department of Electronic Engineering, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, J

Toru Nakura, Department of Electronic Engineering, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, J

Makoto Ikeda, Department of Electronic Engineering, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, J

Kunihiro Asada, Department of Electronic Engineering, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, J

pp. 100-101

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Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique (Abstract)

Roel Pantonial, Graduate School of Engineering, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai, 980-85

Md. Ashfaquzzaman Khan, Graduate School of Engineering, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai, 980-85

Naoto Miyamoto, New Industry Creation Hatchery Center, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai,

Koji Kotani, Graduate School of Engineering, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai, 980-85

Shigetoshi Sugawa, Graduate School of Engineering, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai, 980-85

Tadahiro Ohmi, New Industry Creation Hatchery Center, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai,

pp. 108-109

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Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes (Abstract)

Li-Chun Lin, Department of Electronics Engineering, National Chiao Tung University, Taiwan

Shih-Hao Ou, Department of Electronics Engineering, National Chiao Tung University, Taiwan

Tay-Jyi Lin, Department of Electronics Engineering, National Chiao Tung University, Taiwan

Siang-Den Deng, Department of Electronics Engineering, National Chiao Tung University, Taiwan

Chih-Wei Liu, Department of Electronics Engineering, National Chiao Tung University, Taiwan

pp. 110-111

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A Highly Integrated 8mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16MHz SoC Platform (Abstract)

Huan-Kai Peng, Department of Computer Science, National Tsing Hua University, Taiwan

Chun-Hsin Lee, Department of Computer Science, National Tsing Hua University, Taiwan

Jian-Wen Chen, Department of Computer Science, National Tsing Hua University, Taiwan

Tzu-Jen Lo, Department of Computer Science, National Tsing Hua University, Taiwan

Yung-Hung Chang, Department of Computer Science, National Tsing Hua University, Taiwan

Sheng-Tsung Hsu, Department of Computer Science, National Tsing Hua University, Taiwan

Yuan-Chun Lin, Department of Computer Science, National Tsing Hua University, Taiwan

Ping Chao, Department of Computer Science, National Tsing Hua University, Taiwan

Wei-Cheng Hung, Department of Computer Science, National Tsing Hua University, Taiwan

Kai-Yuan Jan, Department of Computer Science, National Tsing Hua University, Taiwan

pp. 112-113

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Configurable AMBA On-Chip Real-Time Signal Tracer (Abstract)

Chung-Fu Kao, Dept. of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan.

Chi-Hung Lin, Dept. of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan.

Ing-Jer Huang, Dept. of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan.

pp. 114-115

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A Multi-Drop Transmission-Line Interconnect in Si LSI (Abstract)

Junki Seita, Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokoh

Hiroyuki Ito, Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokoh

Kenichi Okada, Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokoh

Takashi Sato, Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokoh

Kazuya Masu, Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokoh

pp. 118-119

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A 90nm 8?16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations (Abstract)

Y. Sugihara, Dept. of Commun.&Comput. Engeineering, Kyoto Univ.

M. Kotani, Dept. of Commun.&Comput. Engeineering, Kyoto Univ.

K. Katsuki, Dept. of Commun.&Comput. Engeineering, Kyoto Univ.

K. Kobayashi, Dept. of Commun.&Comput. Engeineering, Kyoto Univ.

H. Onodera, Dept. of Commun.&Comput. Engeineering, Kyoto Univ.

pp. 122-123

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Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems (Abstract)

Minje Jun, School of Electrical and Electronic Engineering, Yonsei University, Republic of Korea. jjuninho@yons

Kwanhu Bang, School of Electrical and Electronic Engineering, Yonsei University, Republic of Korea. lamar49@yonse

Hyuk-Jun Lee, Cisco Systems Incorporation, U.S.A. hyukjunl@yahoo.com

Naehyuck Chang, School of Computer Science&Engineering, Seoul National University, Republic of Korea. naehyuck@snu.a

Eui-Young Chung, School of Electrical and Electronic Engineering, Yonsei University, Republic of Korea. eychung@yonse

pp. 159-164

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A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses (Abstract)

Bu-Ching Lin, Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan. kurt@eda.ee.

Geeng-Wei Lee, Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan. kurt@eda.ee.

Juinn-Dar Huang, Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan. kurt@eda.ee.

Jing-Yang Jou, Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan. kurt@eda.ee.

pp. 165-170

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Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms (Abstract)

Krishnan Srinivasan, Department of CSE, PO BOX 875406, Arizona State University, Tempe, AZ 85287-5406. Email: ksrinivasan

Karam S. Chatha, Department of CSE, PO BOX 875406, Arizona State University, Tempe, AZ 85287-5406. Email: kchatha@asu

Goran Konjevod, Department of CSE, PO BOX 875406, Arizona State University, Tempe, AZ 85287-5406. Email: goran@asu.e

pp. 184-190

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Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic (Abstract)

Xuexin Liu, ASIC&System State Key Lab., Microelectronics Dept., Fudan University, Shanghai 200433, P.R.China

Wai-Shing Luk, luk@fudan.edu.cn

Yu Song, ASIC&System State Key Lab., Microelectronics Dept., Fudan University, Shanghai 200433, P.R.China

Pushan Tang, ASIC&System State Key Lab., Microelectronics Dept., Fudan University, Shanghai 200433, P.R.China

Xuan Zeng, ASIC&System State Key Lab., Microelectronics Dept., Fudan University, Shanghai 200433, P.R.China

pp. 203-208

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Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM (Abstract)

Jun-Fu Huang, Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu Science-Based Industrial Park, Taiwan, R.

Victor C.Y. Chang, Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu Science-Based Industrial Park, Taiwan, R.

Sally Liu, Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu Science-Based Industrial Park, Taiwan, R.

Kelvin Y.Y. Doong, Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu Science-Based Industrial Park, Taiwan, R.

Keh-Jeng Chang, Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.

pp. 221-225

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Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability (Abstract)

Chung-Wei Lin, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan. enorm

Ming-Chao Tsai, Department of Computer Science, National Tsing Hua University, Hsinchu 300, Taiwan. enorm@eda.ee.ntu

Kuang-Yao Lee, Department of Computer Science, National Tsing Hua University, Hsinchu 300, Taiwan. enorm@eda.ee.ntu

Tai-Chen Chen, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan. tcche

Ting-Chi Wang, Department of Computer Science, National Tsing Hua University, Hsinchu 300, Taiwan. enorm@eda.ee.ntu

Yao-Wen Chang, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan; Depar

pp. 238-243

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DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm (Abstract)

Zhen Cao, Computer Science&Technology Department, Tsinghua University, Beijing 100084, China. Phone: +86-10-62

Tong Jing, Computer Science&Technology Department, Tsinghua University, Beijing 100084, China. Phone: +86-10-62

Jinjun Xiong, Electrical Engineering Department, UCLA, Los Angeles, CA, 90095, USA. Phone: (310) 267-5407; IBM Res

Yu Hu, Electrical Engineering Department, UCLA, Los Angeles, CA, 90095, USA. Phone: (310) 267-5407, e-mail:

Lei He, Electrical Engineering Department, UCLA, Los Angeles, CA, 90095, USA. Phone: (310) 267-5407, e-mail:

Xianlong Hong, Computer Science&Technology Department, Tsinghua University, Beijing 100084, China. Phone: +86-10-62

pp. 256-261

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A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction (Abstract)

Pei-Ci Wu, Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan. g944310@oz.nthu.edu.

Jhih-Rong Gao, Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan. g944310@oz.nthu.edu.

Ting-Chi Wang, Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan. g944310@oz.nthu.edu.

pp. 262-267

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A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks (Abstract)

null Tan Yan, Graduate Sch. of Environ. Eng., Kitakyushu Univ., Fukuoka

null Shuting Li, Graduate Sch. of Environ. Eng., Kitakyushu Univ., Fukuoka

Y. Takashima, Graduate Sch. of Environ. Eng., Kitakyushu Univ., Fukuoka

H. Murata, Graduate Sch. of Environ. Eng., Kitakyushu Univ., Fukuoka

pp. 268-273

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A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units (Abstract)

Takeshi Shiro, Graduate School of Information Science and Technology, Osaka University, 1-5, Yamada-oka, Suita, Osa

Masaaki Abe, Graduate School of Information Science and Technology, Osaka University, 1-5, Yamada-oka, Suita, Osa

Keishi Sakanushi, Graduate School of Information Science and Technology, Osaka University, 1-5, Yamada-oka, Suita, Osa

Yoshinori Takeuchi, Graduate School of Information Science and Technology, Osaka University, 1-5, Yamada-oka, Suita, Osa

Masaharu Imai, Graduate School of Information Science and Technology, Osaka University, 1-5, Yamada-oka, Suita, Osa

pp. 286-291

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Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture (Abstract)

Kentaro Kawakami, Department of Informatics and Electronics, Graduate School of Science and Technology, Kobe Universit

Mitsuhiko Kuroda, Department of Informatics and Electronics, Graduate School of Science and Technology, Kobe Universit

Hiroshi Kawaguchi, Department of Computer and Systems Engineering, Kobe University, Kobe, Hyogo 657-8501. Tel: +81-78-8

Masahiko Yoshimoto, Department of Computer and Systems Engineering, Kobe University, Kobe, Hyogo 657-8501. Tel: +81-78-8

pp. 292-297

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Deeper Bound in BMC by Combining Constant Propagation and Abstraction (Abstract)

Roy Armoni

Limor Fix, Logic and Validation Technology, Intel Corporation, Haifa, Israel

Ranan Fraer, Logic and Validation Technology, Intel Corporation, Haifa, Israel

Tamir Heyman, Logic and Validation Technology, Intel Corporation, Haifa, Israel; Carnegie Mellon University, Pitts

Moshe Vardi, Rich University, Houston, Tx

Yakir Vizel, Logic and Validation Technology, Intel Corporation, Haifa, Israel

Yael Zbar, Logic and Validation Technology, Intel Corporation, Haifa, Israel

pp. 304-309

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Energy-Efficient Real-Time Task Scheduling in Multiprocessor DVS Systems (Abstract)

Jian-Jia Chen, Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiw

Chuan-Yue Yang, Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiw

Tei-Wei Kuo, Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiw

Chi-Sheng Shih, Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiw

pp. 342-349

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Towards scalable and secure execution platform for embedded systems (Abstract)

Inoue Hiroaki, System Devices Research Laboratories, NEC Corporation, 1120, Shimokuzawa, Sagamihara, Kanagawa 229-1

Masato Edahiro, System Devices Research Laboratories, NEC Corporation, 1120, Shimokuzawa, Sagamihara, Kanagawa 229-1

Junji Sakai, System Devices Research Laboratories, NEC Corporation, 1120, Shimokuzawa, Sagamihara, Kanagawa 229-1

pp. 350-354

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Reduced-Order Wide-Band Interconnect Model Realization using Filter-Based Spline Interpolation (Abstract)

Arthur Nieuwoudt, Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. Tel: 713-348-

Mehboob Alam, Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. Tel: 713-348-

Yehia Massoud, Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. Tel: 713-348-

pp. 373-378

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Frequency Selective Model Order Reduction via Spectral Zero Projection (Abstract)

Mehboob Alam, Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. Tel: 713-348-

Arthur Nieuwoudt, Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. Tel: 713-348-

Yehia Massoud, Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. Tel: 713-348-

pp. 379-383

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Abstract, Multifaceted Modeling of Embedded Processors for System Level Design (Abstract)

Gunar Schirner, Center for Embedded Computer Systems, University of California, Irvine, USA. hschirne@cecs.uci.edu

Andreas Gerstlauer, Center for Embedded Computer Systems, University of California, Irvine, USA. gerstl@cecs.uci.edu

Rainer Domer, Center for Embedded Computer Systems, University of California, Irvine, USA. doemer@cecs.uci.edu

pp. 384-389

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BddCut: Towards Scalable Symbolic Cut Enumeration (Abstract)

Andrew C. Ling, Department Electrical and Computer Engineering, University of Toronto, Toronto, Canada. e-mail: alin

Jianwen Zhu, Department Electrical and Computer Engineering, University of Toronto, Toronto, Canada. e-mail: jzhu

Stephen D. Brown, Altera Corporation, Toronto Technology Centre, Toronto, Canada. e-mail: sbrown@altera.com

pp. 408-413

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Node Mergers in the Presence of Don't Cares (Abstract)

Stephen M. Plaza, EECS Department, University of Michigan, Ann Arbor, MI 48109-2121. splaza@umich.edu

Kai-hui Chang, EECS Department, University of Michigan, Ann Arbor, MI 48109-2121. changkh@umich.edu

Igor L. Markov, EECS Department, University of Michigan, Ann Arbor, MI 48109-2121. imarkov@umich.edu

Valeria Bertacco, EECS Department, University of Michigan, Ann Arbor, MI 48109-2121. valeria@umich.edu

pp. 414-419

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A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects (Abstract)

Ying Zhou, Department of Electrical Engineering, Texas A&M University, College Station, Texas 77843

Zhuo Li, Pextra Corporation, 2900B Longmire Drive, College Station, Texas 77845

Yuxin Tian, Department of Electrical Engineering, Texas A&M University, College Station, Texas 77843

Weiping Shi, Department of Electrical Engineering, Texas A&M University, College Station, Texas 77843

Frank Liu, IBM Austin Research Laboratory, 11501 Burnet Rd., Austin, Texas 78758

pp. 450-455

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Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method (Abstract)

Alexander Mitev, Electrical Engineering Department, University of Arizona, Tucson, AZ - 85716. Tel: 520-621-2434, Fax

Michael Marefat, Electrical Engineering Department, University of Arizona, Tucson, AZ - 85716. Tel: 520-621-2434, Fax

Dongsheng Ma, Electrical Engineering Department, University of Arizona, Tucson, AZ - 85716. Tel: 520-621-2434, Fax

Janet Wang, Electrical Engineering Department, University of Arizona, Tucson, AZ - 85716. Tel: 520-621-2434, Fax

pp. 468-473

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Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations (Abstract)

Jun Tao, ASIC&System State Key Lab., Microelectronics Dept., Fudan University, Shanghai 200433, P.R. China

Xuan Zeng, ASIC&System State Key Lab., Microelectronics Dept., Fudan University, Shanghai 200433, P.R. China. x

Wei Cai, Department of Mathematics, University of North Carolina, Charlotte, Charlotte, NC 28233, USA

Yangfeng Su, Mathematics Dept., Fudan University, Shanghai 200433, P.R. China

Dian Zhou, ASIC&System State Key Lab., Microelectronics Dept., Fudan University, Shanghai 200433, P.R. China; E

Charles Chiang, Advanced Technology Group, Synopsys Inc., Mountain View, CA 94043, USA

pp. 474-479

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Signal-to-Memory Mapping Analysis for Multimedia Signal Processing (Abstract)

Ilie I. Luican, Dept. of Computer Science, University of Illinois, Chicago, Chicago, IL 60607, U.S.A.

Hongwei Zhu, Dept. of Computer Science, University of Illinois, Chicago, Chicago, IL 60607, U.S.A.

Florin Balasa, Dept. of Computer Science, University of Illinois, Chicago, Chicago, IL 60607, U.S.A.

pp. 486-491

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MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip (Abstract)

T.S. Rajesh Kumar, Texas Instruments India Ltd., C.V. Raman Nagar, Bangalore, 560 091, India. srk@ti.com

C.P. Ravikumar, Texas Instruments India Ltd., C.V. Raman Nagar, Bangalore, 560 091, India. ravikumar@ti.com

R. Govindarajan, Supercomputer Education&Research Centre, Indian Institute of Science, Bangalore, 560 012, India. gov

pp. 492-497

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A Run-Time Memory Protection Methodology (Abstract)

Udaya Seshua, NXP Semiconductors, BL Personal, Millenia `D' Block, # 1, Murphy Road, Ulsoor 560008, Bangalore, Ind

Nagaraju Bussa, Philips Research, Philips Innovation Campus, # 1, Murphy Road, Ulsoor 560008, Bangalore, India. naga

Bart Vermeulen, NXP Semiconductors, Research, High Tech Campus 5, 5656 AE Eindhoven, The Netherlands. bart.vermeulen

pp. 498-503

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Short-Circuit Compiler Transformation: Optimizing Conditional Blocks (Abstract)

Mohammad Ali Ghodrat, Department of Computer Sciences, Center for Embedded Computer Systems, University of California, Irv

Tony Givargis, Department of Computer Sciences, Center for Embedded Computer Systems, University of California, Irv

Alex Nicolau, Department of Computer Sciences, Center for Embedded Computer Systems, University of California, Irv

pp. 504-510

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Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection (Abstract)

M. A. Ochoa-Montiel, ESD, School of ECS, University of Southampton, Southampton, UK. mao02r@ecs.soton.ac.uk

B. M. Al-Hashimi, ESD, School of ECS, University of Southampton, Southampton, UK. bmah@ecs.soton.ac.uk

P. Kollig, Home Innovation Centre Southampton, NXP Semiconductors, Southampton, UK

pp. 517-522

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High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs (Abstract)

Deming Chen, Department of ECE, University of Illinois, Urbana-Champaign. dchen@uiuc.edu

Jason Cong, Computer Science Department, University of California, Los Angeles. cong@cs.ucla.edu

Yiping Fan, Computer Science Department, University of California, Los Angeles. fanyp@cs.ucla.edu

Zhiru Zhang, Computer Science Department, University of California, Los Angeles. zhiruz@cs.ucla.edu

pp. 529-534

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Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies (Abstract)

Zhangcai Huang, Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, 808-0135 Japa

Hong Yu, Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, 808-0135 Japa

Atsushi Kurokawa, Sanyo Semiconductor Co., Ltd, Gunma, 370-0596 Japan

Yasuaki Inoue, Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, 808-0135 Japa

pp. 565-570

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Flow-Through-Queue based Power Management for Gigabit Ethernet Controller (Abstract)

Hwisung Jung, Dept. of Electrical Engineering, University of Southern California, Los Angeles, CA 90089. e-mail: h

Andy Hwang, Enterprise Networking Group, Broadcom Corporation, Irvine, CA 92618. e-mail: ahwang@broadcom.com

Massoud Pedram, Dept. of Electrical Engineering, University of Southern California, Los Angeles, CA 90089. e-mail: p

pp. 571-576

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Development of Low Power ISDB-T One-Segment Decoder by Mobile Multi-Media Engine SoC (S1G) (Abstract)

K. Mori, Toshiba Corporation Semiconductor Company, 580-1 Horikawa-Cho, Saiwai-ku, Kawasaki 212-8520, Japan

M. Suzuki, Toshiba Corporation Digital Media Network Company, 2-9 Suehiro-Cho, Ome, Tokyo 198-8710, Japan

Y. Ohara, Toshiba Corporation Semiconductor Company, 580-1 Horikawa-Cho, Saiwai-ku, Kawasaki 212-8520, Japan

S. Matsuo, Toshiba Corporation Semiconductor Company, 580-1 Horikawa-Cho, Saiwai-ku, Kawasaki 212-8520, Japan

A. Asano, Toshiba Corporation Digital Media Network Company, 2-9 Suehiro-Cho, Ome, Tokyo 198-8710, Japan

pp. 644-648

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Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier" (Abstract)

Masaitsu Nakajima, Strategic Semiconductor Development Center, Matsushita Electric Industrial Co., Ltd, 3-1-1 Yagumo-Na

Takao Yamamoto, Strategic Semiconductor Development Center, Matsushita Electric Industrial Co., Ltd, 3-1-1 Yagumo-Na

Masayuki Yamasaki, Strategic Semiconductor Development Center, Matsushita Electric Industrial Co., Ltd, 3-1-1 Yagumo-Na

Tetsu Hosoki, Strategic Semiconductor Development Center, Matsushita Electric Industrial Co., Ltd, 3-1-1 Yagumo-Na

Masaya Sumita, 1 Kotari-Yakemachi Nagaokakyo, Kyoto, 617-8520 Japan

pp. 649-653

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Logic and Layout Aware Voltage Island Generation for Low Power Design (Abstract)

Liangpeng Guo, EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, China

Yici Cai, EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, China

Qiang Zhou, EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, China

Xianlong Hong, EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, China

pp. 666-671

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Delay Uncertainty Reduction by Interconnect and Gate Splitting (Abstract)

Vineet Agarwal, Electrical and Computer Engineering Department, University of Arizona, Tucson, AZ - 85721. Tel: 520-

Jin Sun, Electrical and Computer Engineering Department, University of Arizona, Tucson, AZ - 85721. Tel: 520-

Alexander Mitev, Electrical and Computer Engineering Department, University of Arizona, Tucson, AZ - 85721. Tel: 520-

Janet Wang, Electrical and Computer Engineering Department, University of Arizona, Tucson, AZ - 85721. Tel: 520-

pp. 690-695

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Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect (Abstract)

Arthur Nieuwoudt, Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. Tel: 713-348-

Mosin Mondal, Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. Tel: 713-348-

Yehia Massoud, Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. Tel: 713-348-

pp. 708-713

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Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores (Abstract)

Dan Zhao, Center for Advanced Computer Studies, University at Louisiana, Lafayette, Lafayette, LA 70504-4330,

Unni Chandran, Center for Advanced Computer Studies, University at Louisiana, Lafayette, Lafayette, LA 70504-4330,

Hideo Fujiwara, Graduate School of Information Science, Nara Institute of Science and Technology, Ikoma, Nara 630-01

pp. 714-719

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Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses (Abstract)

Fawnizu Azmadi Hussin, Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science Cit

Tomokazu Yoneda, Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science Cit

Alex Orailoglu, Computer Science and Engineering Department, University of California, San Diego, La Jolla, CA 92093

Hideo Fujiwara, Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science Cit

pp. 720-725

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RunBasedReordering: A Novel Approach for Test Data Compression and Scan Power (Abstract)

Hao Fang, Micro Processor Research and Development Center of Peking University, Beijing, China, 100871. Tel: 0

Chenguang Tong, Micro Processor Research and Development Center of Peking University, Beijing, China, 100871. Tel: 0

Xu Cheng, Micro Processor Research and Development Center of Peking University, Beijing, China, 100871. Tel: 0

pp. 732-737

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Configurable Multi-Processor Platforms for Next Generation Embedded Systems (Abstract)

David Goodwin, Tensilica Inc., Santa Clara CA 95054. Tel: +1-123-456-7890, Fax: +1-408-986-8919, e-mail: goodwin@te

Chris Rowen, Tensilica Inc., Santa Clara CA 95054. Tel: +1-408-327-7333, Fax: +1-408-986-8919, e-mail: rowen@tens

Grant Martin, Tensilica Inc., Santa Clara CA 95054. Tel: +1-408-327-7323, Fax: +1-408-986-8919, e-mail: gmartin@te

pp. 744-746

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Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach (Abstract)

null Le Kang, Dept. of Comput. Sci.&Technol., Tsinghua Univ., Beijing

null Yici Cai, Dept. of Comput. Sci.&Technol., Tsinghua Univ., Beijing

null Yi Zou, Dept. of Comput. Sci.&Technol., Tsinghua Univ., Beijing

null Jin Shi, Dept. of Comput. Sci.&Technol., Tsinghua Univ., Beijing

null Xianlong Hong, Dept. of Comput. Sci.&Technol., Tsinghua Univ., Beijing

S.X.-D. Tan

pp. 751-756

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A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms (Abstract)

Hanif Fatemi, EE-Systems Dept., University of Southern California, Los Angeles, CA 90089. fatemi@usc.edu

Shahin Nazarian, EE-Systems Dept., University of Southern California, Los Angeles, CA 90089. shahin@usc.edu

Massoud Pedram, EE-Systems Dept., University of Southern California, Los Angeles, CA 90089. pedram@usc.edu

pp. 774-779

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Thermal-Aware 3D IC Placement Via Transformation (Abstract)

Jason Cong, Department of Computer Science, University of California, Los Angeles, Los Angeles, CA 90095. Email:

Guojie Luo, Department of Computer Science, University of California, Los Angeles, Los Angeles, CA 90095. Email:

Jie Wei, Department of Computer Science, University of California, Los Angeles, Los Angeles, CA 90095. Email:

Yan Zhang, Department of Computer Science, University of California, Los Angeles, Los Angeles, CA 90095. Email:

pp. 780-785

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On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design (Abstract)

Chao-Hung Lu, Department of Electrical Engineering, National Central University, Taoyuan, Taiwan, R.O.C. Email: ch

Hung-Ming Chen, E.E. Department and SoC Research Center, National Chiao Tung University, Hsinchu, Taiwan. Email: hmc

Chien-Nan Jimmy Liu, Department of Electrical Engineering, National Central University, Taoyuan, Taiwan, R.O.C. Email: ji

pp. 792-797

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Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign (Abstract)

Ren-Jie Lee, Department of Electronics Engineering and SoC Research Center, National Chiao Tung University, Hsinc

Ming-Fang Lai, Department of Electronics Engineering and SoC Research Center, National Chiao Tung University, Hsinc

Hung-Ming Chen, Department of Electronics Engineering and SoC Research Center, National Chiao Tung University, Hsinc

pp. 804-809

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Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes (Abstract)

Zhuo Zhang, Dept. of ECE, University of Iowa, Iowa City, IA 52242. zhuzhang@engineering.uiowa.edu

Sudhakar M. Reddy, Dept. of ECE, University of Iowa, Iowa City, IA 52242. reddy@engineering.uiowa.edu

Irith Pomeranz, School of ECE, Purdue University, Wet Lafayette, IN 47907. pomeranz@ecn.purdue.edu

pp. 817-822

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Preferable Improvements and Changes to FB-DiMM High-Speed Channel for 9.6Gbps Operation (Abstract)

Atsushi Hiraishi, Elpida Memory, Inc. Technology&Development Office, 3-1-35 Minamihashimoto, Sagamihara, Kanagawa, 229

Toshio Sugano, Elpida Memory, Inc. Technology&Development Office, 3-1-35 Minamihashimoto, Sagamihara, Kanagawa, 229

Hideki Kusamitsu, Yamaichi Electronics co., Ltd. 3-28-7 Nakaumagome, Otaku, Tokyo, 143-8515 Japan. e-mail: kusamitsu@y

pp. 841-845

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Design Consideration of 6.25 Gbps Signaling for High-Performance Server (Abstract)

Jian Hong Jiang, Platform Innovation Group, Fujitsu Laboratories of America, Inc., 1240 East Arques Avenue, Sunnyvale

Weixin Gai, Platform Innovation Group, Fujitsu Laboratories of America, Inc., 1240 East Arques Avenue, Sunnyvale

Akira Hattori, Platform Innovation Group, Fujitsu Laboratories of America, Inc., 1240 East Arques Avenue, Sunnyvale

Yasuo Hidaka, Platform Innovation Group, Fujitsu Laboratories of America, Inc., 1240 East Arques Avenue, Sunnyvale

Takeshi Horie, Platform Innovation Group, Fujitsu Laboratories of America, Inc., 1240 East Arques Avenue, Sunnyvale

Yoichi Koyanagi, Platform Innovation Group, Fujitsu Laboratories of America, Inc., 1240 East Arques Avenue, Sunnyvale

Hideki Osone, Platform Innovation Group, Fujitsu Laboratories of America, Inc., 1240 East Arques Avenue, Sunnyvale

pp. 854-857

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System Co-Design and Co-Analysis Approach to Implementing the XDR? Memory System of the Cell Broadband Engine? Processor; Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume Production (Abstract)

Wai-Yeung Yip, Platform Solutions, Rambus Inc, Los Altos, CA 94022. Tel: 650-947-5000, Fax: 650-947-5001, e-mail: w

Scott Best, Architecture, Rambus Inc, Los Altos, CA 94022. Tel: 650-947-5000, Fax: 650-947-5001, e-mail: sbest@r

Wendemagegnehu Beyene, Signal Integrity, Rambus Inc, Los Altos, CA 94022. Tel: 650-947-5000, Fax: 650-947-5001, e-mail: wbe

Ralf Schmitt, Signal Integrity, Rambus Inc, Los Altos, CA 94022. Tel: 650-947-5000, Fax: 650-947-5001, e-mail: rsc

pp. 858-865

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Flow Time Minimization under Energy Constraints (Abstract)

Jian-Jia Chen, Department of Computer Science and Information Engineering, National Taiwan University, Taiwan. r900

Kazuo Iwama, School of Informatics, Kyoto University, Yoshida-Honmachi, Kyoto, Japan. iwama@kuis.kyoto-u.ac.jp

Tei-Wei Kuo, Department of Computer Science and Information Engineering, National Taiwan University, Taiwan. ktw@

Hseuh-I Lu, Department of Computer Science and Information Engineering, National Taiwan University, Taiwan. hil@

pp. 866-871

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A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation (Abstract)

Maziar Goudarzi, System LSI Research Center, Kyushu University, Fukuoka, Japan. Tel: +81-92-847-5193, Fax: +81-92-847

Tohru Ishihara, System LSI Research Center, Kyushu University, Fukuoka, Japan. Tel: +81-92-847-5193, Fax: +81-92-847

Hiroto Yasuura, System LSI Research Center, Kyushu University, Fukuoka, Japan. Tel: +81-92-847-5193, Fax: +81-92-847

pp. 878-883

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Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency (Abstract)

Subhasis Banerjee, Diagnostics Engineering Group, Sun Microsystems, Bangalore, INDIA. E-mail: subhasis.banerjee@sun.com

Surendra G, CAD Laboratory, Supercomputer Education and Research Centre, Indian Institute of Science, Bangalore,

S. K. Nandy, CAD Laboratory, Supercomputer Education and Research Centre, Indian Institute of Science, Bangalore,

pp. 884-889

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Design Methodology for 2.4GHz Dual-Core Microprocessor (Abstract)

Noriyuki Ito, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan. ito.noriyuki@jp.fujitsu

Hiroaki Komatsu, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan

Akira Kanuma, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan

Akihiro Yoshitake, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan

Yoshiyasu Tanamura, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan

Hiroyuki Sugiyama, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan

Ryoichi Yamashita, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan

Ken-ichi Nabeya, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan

Hironobu Yoshino, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan

Hitoshi Yamanaka, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan

Masahiro Yanagida, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan

Yoshitomo Ozeki, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan

Kinya Ishizaka, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan

Takeshi Kono, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan

Yutaka Isoda, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan

pp. 896-901

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A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications (Abstract)

Zhenyu Liu, School of Engineering and Electronic, The University of Edinburgh, Edinburgh, EH9 3JL, UK. e-mail: z

Tughrul Arslan, School of Engineering and Electronic, The University of Edinburgh Edinburgh, EH9 3JL, UK. e-mail: T.

Ahmet T. Erdogan, School of Engineering and Electronic, The University of Edinburgh Edinburgh, EH9 3JL, UK. e-mail: Ah

pp. 908-913

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Multithreaded SAT Solving (Abstract)

Matthew Lewis, Institute for Computer Science, Albert-Ludwigs-University of Freiburg, Georges-Koehler-Allee 51, 791

Tobias Schubert, Institute for Computer Science, Albert-Ludwigs-University of Freiburg, Georges-Koehler-Allee 51, 791

Bernd Becker, Institute for Computer Science, Albert-Ludwigs-University of Freiburg, Georges-Koehler-Allee 51, 791

pp. 926-931

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Trace Compaction using SAT-based Reachability Analysis (Abstract)

Sean Safarpour, Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada. sean@eecg

Andreas Veneris, Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada. veneris@e

Hratch Mangassarian, Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada. hratch@ee

pp. 932-937

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