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Asia and South Pacific Design Automation Conference 2000 (ASP-DAC'00)
Yokohama, Japan
January 25-January 28
ISBN: 0-7803-5973-9
Table of Contents
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Session A1 (Special Session): University LSI Design Contest
Michael C.-J. Lin, National Tsing Hua University, Taiwan
Youn-Long Lin, National Tsing Hua University, Taiwan
pp. 1
Oliver Leung, Hong Kong University of Science and Technology
Chi-ying Tsui, Hong Kong University of Science and Technology
Roger S. Cheng, Hong Kong University of Science and Technology
pp. 3
Chi-Ying Tsui, Hong Kong University of Science and Technology, Clear Water Bay
Louis Chung-Yin Kwan, Hong Kong University of Science and Technology, Clear Water Bay
Chin-Tau Lea, Hong Kong University of Science and Technology, Clear Water Bay
pp. 5
J.-K. Lee, Dongshin University, Korea
S.-M. Lee, Dongshin University, Korea
M. M.-O. Lee, Dongshin University, Korea
D.-W. Lee, Chonnam National University, Korea
Y.-C. Kim, Chonnam National University, Korea
S.-J. Jeong, Chonnam National University, Korea
pp. 7
Shin'ichi Wakabayashi, Hiroshima University, Japan
Tetsushi Koide, The University of Tokyo, Japan
Naoyoshi Toshine, Hiroshima University, Japan
Masataka Yamane, Hiroshima University, Japan
Hajime Ueno, Hiroshima University, Japan
pp. 9
Chih-Tsun Huang, National Tsing Hua University, Taiwan
Jing-Reng Huang, National Tsing Hua University, Taiwan
Cheng-Wen Wu, National Tsing Hua University, Taiwan
pp. 11
Fan Mo, Fudan University, Shanghai, China
Yihua Zhang, Fudan University, Shanghai, China
Jun Yu, Fudan University, Shanghai, China
Qianling Zhang, Fudan University, Shanghai, China
pp. 13
Tin-Yau Tang, The Chinese University of Hong Kong
Chiu-Sing Choy, The Chinese University of Hong Kong
Pui-Lam Siu, The Chinese University of Hong Kong
Cheong-Fat Chan, The Chinese University of Hong Kong
pp. 15
Seung-Min Lee, Dongshin University, Korea
Jin -Hong Chung, Dongshin University, Korea
Hyung-Seok Yoon, Dongshin University, Korea
Mike Myung-Ok Lee, Dongshin University, Korea
pp. 17
Noriaki Takeda, Hiroshima University, Japan
Mituru Homma, Hiroshima University, Japan
Makoto Nagata, Hiroshima University, Japan
Takashi Morie, Hiroshima University, Japan
Atsushi Iwata, Hiroshima University, Japan
pp. 19
Tomohiro Nezuka, University of Tokyo, Japan
Takafumi Fujita, University of Tokyo, Japan
Makoto Ikeda, University of Tokyo, Japan
Kunihiro Asada, University of Tokyo, Japan
pp. 21
Kenichi Murakoshi, Hiroshima University, Japan
Takashi Morie, Hiroshima University, Japan
Makoto Nagata, Hiroshima University, Japan
Atsushi Iwata, Hiroshima University, Japan
pp. 23
Shinji Kimura, Nara Institute of Science and Technology, Japan
Hiroyuki Kida, NIIT at Nara, Japan
Kazuyoshi Takagi, Nagoya University
Tatsumori Abematsu, SHARP Corporation
Katsumasa Watanabe, Nara Institute of Science and Technology, Japan
pp. 25
Hiroshi Sasaki, Tohoku University, Japan
Hitoshi Maruyama, Tohoku University, Japan
Hiroaki Kobayashi, Tohoku University, Japan
Tadao Nakamura, Tohoku University, Japan
Hideaki Tsukioka, Friendly Systems Co., Ltd., Japan
Nobuyoshi Shoji, Friendly Systems Co., Ltd., Japan
pp. 27
Naoki Nishimura, Hiroshima City University, Japan
Takahiro Sasaki, Hiroshima City University, Japan
Tetsuo Hironaka, Hiroshima City University, Japan
pp. 29
Hirofumi Sakamoto, Hiroshima City University, Japan
Hiroyuki Ochi, Hiroshima City University, Japan
Ken'ichiro Uda, Kobe University, Japan
Kazuo Taki, Kobe University, Japan
Bu-Yeol Lee, Kobe University, Japan
Takao Tsuda, Kobe University, Japan
pp. 33
Joonho Lim, Global Communication Technology, Inc., CA
Dong-Gyu Kim, Daewoo Electronics Ltd., Seoul, Korea
Sang-Chul Kang, Seoul National University, Seoul, Korea
Soo-Ik Chae, Seoul National University, Seoul, Korea
pp. 35
Session B1: IP Reuse and Protection Methods
Daniel D. Gajski, University of California, Irvine, USA
Allen C.-H. Wu, Tsing Hua University, Taiwan, ROC
Viraphol Chaiyakul, Y Explorations Inc., USA
Shojiro Mori, Toshiba Corp., Japan
Tom Nukiyama, NEC Corp., Japan
Pierre Bricaud, Mentor Graphics Corp., USA
pp. 37
Nong Fan, Y Explorations, Inc., Lake Forest, CA
Viraphol Chaiyakul, Y Explorations, Inc., Lake Forest, CA
Daniel D. Gajski, University of California, Irvine
pp. 43
Gang Qu, University of California, Los Angeles
Jennifer L. Wong, University of California, Los Angeles
Miodrag Potkonjak, University of California, Los Angeles
pp. 55
Session C1: Decision Diagrams and Verification Methods
Rajarshi Mukherjee, Fujitsu Laboratories of America, Sunnyvale, CA
Jawahar Jain, Fujitsu Laboratories of America, Sunnyvale, CA
Koichiro Takayama, Fujitsu Laboratories of America, Sunnyvale, CA
Masahiro Fujita, Fujitsu Laboratories of America, Sunnyvale, CA
pp. 67
Yukihiro Iguchi, Meiji University, Japan
Munehiro Matsuura, Kyushu Institute of Technology, Japan
Tsutomu Sasao, Kyushu Institute of Technology, Japan
Atsumu Iseno, Meiji University, Japan
pp. 73
Subir K. Roy, Fujitsu Laboratories Ltd., Japan
Hiroaki Iwashita, Fujitsu Laboratories Ltd., Japan
Tsuneo Nakata, Fujitsu Laboratories Ltd., Japan
pp. 77
Kazuhiro Nakamura, Nara Institute of Science and Technology, Japan
Shinji Maruoka, Nara Institute of Science and Technology, Japan
Shinji Kimura, Nara Institute of Science and Technology, Japan
Katsumasa Watanabe, Nara Institute of Science and Technology, Japan
pp. 81
Session D1: Routing in Deep-Submicron
Yukiko Kubo, Tokyo Inst. of Technology, Japan
Yasuhiro Takashima, Japan Advanced Inst. of Science and Technology, Japan
Shigetoshi Nakatake, Kitakyushu University, Japan
Yoji Kajitani, Tokyo Inst. of Technology, Japan
pp. 87
Zhang Yan, Tsinghua University, P.R. China
Wang Baohua, Tsinghua University, P.R. China
Cai Yici, Tsinghua University, P.R. China
Hong Xianlong, Tsinghua University, P.R. China
pp. 105
Session A2 (Special Session): CAD for Embedded Systems
Stephen S. Brown, The University of California at Los Angeles
Jeet Asher, The University of California at Los Angeles
William H. Mangione-Smith, The University of California at Los Angeles
pp. 111
Dinesh Ramanathan, University of California, Irvine
Ravindra Jejurikar, University of California, Irvine
Rajesh K. Gupta, University of California, Irvine
pp. 117
Yuan Xie, Princeton University, NJ
Wayne Wolf, Princeton University, NJ
pp. 129
Session B2: System-Level Power Optimization & Estimation
Heng-Liang Huang, National Chiao-Tung University, Taiwan
Jiing-Yuan Lin, Global UniChip Corporation, Taiwan
Wen-Zen Shen, National Chiao-Tung University, Taiwan
Jing-Yang Jou, National Chiao-Tung University, Taiwan
pp. 135
Tony D. Givargis, University of California, Riverside
Frank Vahid, University of California, Riverside
J? Henkel, NEC USA, NJ
pp. 141
Session C2: Design Environment for FPGA
Jason Cong, University of California, Los Angeles
Songjie Xu, Aplus Design Technologies, Inc., Los Angeles
pp. 157
R. Hartenstein, University of Kaiserslautern, Germany
M. Herz, University of Kaiserslautern, Germany
Th. Hoffmann, University of Kaiserslautern, Germany
U. Nageldinger, University of Kaiserslautern, Germany
pp. 163
Byungil Jeong, Seoul National University, Korea
Sungjoo Yoo, Seoul National University, Korea
Sunghyun Lee, Seoul National University, Korea
Kiyoung Choi, Seoul National University, Korea
pp. 169
Session D2: Placement Consistent with Routing
Andrew Kennings, University of Waterloo, Canada
Igor Markov, UCLA Computer Science, Los Angeles, CA
pp. 179
Session E2 (Special Session): System-In-Package (SIP)
Michael X. Wang, University of California, Santa Cruz
Katsuharu Suzuki, University of California, Santa Cruz
Wayne W.-M. Dai, University of California, Santa Cruz
Yee L. Low, Lucent Technologies, Murray Hill, NJ
Kevin J. O'conner, Lucent Technologies, Murray Hill, NJ
King L. Tai, Lucent Technologies, Murray Hill, NJ
pp. 205
Session A3: Low Power Design : Implementation
Youngsoo Shin, Seoul National University, Korea
Kiyoung Choi, Seoul National University, Korea
pp. 217
Session B3: Embedded Software
Ing-Jer Huang, National Sun Yat-sen University, Kaohsiung, Taiwan
Dao-Zhen Chen, National Sun Yat-sen University, Kaohsiung, Taiwan
pp. 229
Johnson Kin, University of California at Los Angeles
Chunho Lee, University of California at Los Angeles
William H. Mangione-Smith, University of California at Los Angeles
Miodrag Potkonjak, University of California at Los Angeles
pp. 241
Session C3: Implementation of Boolean Functions
Shigeru Yamashita, NTT Communication Science Laboratories, Japan
Hiroshi Sawada, NTT Communication Science Laboratories, Japan
Akira Nagoya, NTT Communication Science Laboratories, Japan
pp. 253
Tsutomu Sasao, Kyushu Institute of Technology, Japan
Ken-ichi Kurimoto, Kyushu Institute of Technology, Japan
pp. 259
Session D3: Physical Design Planning
Jun Kikuchi, Enterprise Server Division, HITACHI, Ltd.
Tetsuo Sasaki, Enterprise Server Division, HITACHI, Ltd.
Kazuhisa Miyamoto, Enterprise Server Division, HITACHI, Ltd.
Tohru Hashimoto, HITACHI Information Technology Co., Ltd.
pp. 265
Hong Yu, Tsinghua University, Beijing, P. R. China
Xianlong Hong, Tsinghua University, Beijing, P. R. China
Yici Cai, Tsinghua University, Beijing, P. R. China
pp. 271
Jason Cong, University of California, Los Angeles
Tianming Kong, University of California, Los Angeles
Faming Liang, University of California, Los Angeles
Jun S. Liu, Stanford University, CA
Wing Hung Wong, University of California, Los Angeles
Dongmin Xu, University of California, Los Angeles
pp. 277
Session E3: Methodologies for Reliable Design
Yoshiyuki Kawakami, Matsushita Electric Industrial Co., Ltd., Osaka, Japan
Jingkun Fang, BTA Technology, Inc., San Jose, CA
Hirokazu Yonezawa, Matsushita Electric Industrial Co., Ltd., Osaka, Japan
Nobufusa Iwanishi, Matsushita Electric Industrial Co., Ltd., Osaka, Japan
Lifeng Wu, BTA Technology, Inc., San Jose, CA
Alvin I-Hsien Chen, BTA Technology, Inc., San Jose, CA
Norio Koike, Matsushita Electronics Corporation, Kyoto, Japan
Ping Chen, BTA Technology, Inc., San Jose, CA
Chune-Sin Yeh, BTA Technology, Inc., San Jose, CA
Zhihong Liu, BTA Technology, Inc., San Jose, CA
pp. 289
Session A4: Synthesis for System-On-A-Chip
Mizuki Takahashi, Osaka University, Japan; Sharp Corporation, Japan
Nagisa Ishiura, Osaka University, Japan
Akihisa Yamada, Sharp Corporation, Japan
Takashi Kambe, Sharp Corporation, Japan
pp. 303
Nozomu Togawa, Waseda University, Japan
Masayuki Ienaga, Waseda University, Japan
Masao Yanagisawa, Waseda University, Japan
Tatsuo Ohtsuki, Waseda University, Japan
pp. 309
Taewhan Kim, Korea Advanced Institute of Science & Technology
Junhyung Um, Korea Advanced Institute of Science & Technology
pp. 313
Session B4: Reconfiguration Computation
Norbert Imlig, NTT Network Innovation Laboratories, Japan
Ryusuke Konishi, NTT Network Innovation Laboratories, Japan
Tsunemichi Shiozawa, NTT Network Innovation Laboratories, Japan
Kiyoshi Oguri, NTT Network Innovation Laboratories, Japan
Kouichi Nagami, NTT Network Innovation Laboratories, Japan
Hideyuki Ito, NTT Network Innovation Laboratories, Japan
Minoru Inamori, NTT Network Innovation Laboratories, Japan
Hiroshi Nakada, NTT Network Innovation Laboratories, Japan
pp. 317
Session C4: Synthesis for Low Power
Chunhong Chen, Northwestern University, Evanston, IL
Majid Sarrafzadeh, Northwestern University, Evanston, IL
pp. 333
Xunwei Wu, Ningbo University, China
Jian Wei, Ningbo University, China
Massoud Pedram, University of Southern California, Los Angeles
Qing Wu, University of Southern California, Los Angeles
pp. 345
Session D4 (Panel Discussion): Timing Closure : The Solution and Its Problems
Session E4: MOSFET Device Optimization
M. Tanaka, Hiroshima University, Japan
N. Tokida, Hiroshima University, Japan
T. Okagaki, Hiroshima University, Japan
M. Miura-Mattausch, Hiroshima University, Japan
W. Hansch, Universit?t der Bundesweher, Germany
H. J. Mattausch, Hiroshima University, Japan
pp. 365
Mikako Miyama, Semiconductor & Integrated Circuits, Hitachi, Ltd.
Shiro Kamohara, Semiconductor & Integrated Circuits, Hitachi, Ltd.
pp. 371
Andrzej J. Strojwas, Carnegie Mellon University, Pittsburgh, PA; PDF Solutions, Inc., San Jose, CA
pp. 375
Session A5: Low Power Design : System Approach
Qing Wu, University of Southern California, Los Angeles
Qinru Qiu, University of Southern California, Los Angeles
Massoud Pedram, University of Southern California, Los Angeles
pp. 387
Session B5: System Design and Debugging
Inki Hong, University of California, Los Angeles
Darko Kirovski, University of California, Los Angeles
Miodrag Potkonjak, University of California, Los Angeles
Marios C. Papefthymiou, University of Michigan, Ann Arbor
pp. 397
Sang-Joon Nam, Korea Advanced Institute of Science and Technology, Korea
Jun-Hee Lee, Korea Advanced Institute of Science and Technology, Korea
Byoung-Woon Kim, Korea Advanced Institute of Science and Technology, Korea
Yeon-Ho Im, Korea Advanced Institute of Science and Technology, Korea
Young-Su Kwon, Korea Advanced Institute of Science and Technology, Korea
Chong-Min Kyung, Korea Advanced Institute of Science and Technology, Korea
Kyong-Gu Kang, Medison Corporation, Korea
pp. 401
Session C5: Optimization Issues in Logic Synthesis
Wangning Long, Tsinghua University, Beijing, China
Yu-Liang Wu, The Chinese University of HK, Shatin, Hong Kong
Jinian Bian, Tsinghua University, Beijing, China
pp. 415
Session D5: Novel Techniques in Advanced Partitioning
Jason Cong, UCLA Department of Computer Science, Los Angeles, CA
Sung Kyu Lim, UCLA Department of Computer Science, Los Angeles, CA
pp. 429
Hsun-Cheng Lee, Chung Yuan Christian University, Chungli, Taiwan
Ting-Chi Wang, Chung Yuan Christian University, Chungli, Taiwan
pp. 435
Jason Cong, UCLA Department of Computer Science, Los Angeles, CA
Sung Kyu Lim, UCLA Department of Computer Science, Los Angeles, CA
pp. 441
Session E5: Efficient Estimation for Interconnection
Jiangchun Gu, Tsinghua University, Beijing, P. R. China
Zeyi Wang, Tsinghua University, Beijing, P. R. China
Xianlong Hong, Tsinghua University, Beijing, P. R. China
pp. 447
Xiaodong Yang, University of California, San Diego
Walter H. Ku, University of California, San Diego
Chung-Kuan Cheng, University of California, San Diego
pp. 463
Session A6: Optimized LSI Design
Yuan-Pao Hsu, National Chung Cheng University, Taiwan
Kao-Shing Hwang, National Chung Cheng University, Taiwan
Chien-Yuan Pao, National Chung Cheng University, Taiwan
Jinn-Shyan Wang, National Chung Cheng University, Taiwan
pp. 481
Session B6: DSP and Memory Architecture
Naji Ghazal, University of California, Berkeley
Richard Newton, University of California, Berkeley
Jan Rabaey, University of California, Berkeley
pp. 485
Hyunok Oh, Seoul National University, Korea
Soonhoi Ha, Seoul National University, Korea
pp. 491
Hong-Kai Chang, National Tsing Hua University, Taiwan
Youn-Long Lin, National Tsing Hua University, Taiwan
pp. 497
Session C6: Validation and Test
Nina Saxena, University of Texas at Austin
Jacob A. Abraham, University of Texas at Austin
Avijit Saha, IBM, Austin TX
pp. 503
Yoshinobu Higami, Ehime University, Matsuyama, Japan
Yuzo Takamatsu, Ehime University, Matsuyama, Japan
Kewal K. Saluja, University of Wisconsin, Madison
Kozo Kinoshita, Osaka University, Japan
pp. 509
Session D6: Cell Generation & Process Dependent Issues
Kazuhisa Okada, Sharp corporation, Japan
Takayuki Yamanouchi, Sharp corporation, Japan
Takashi Kambe, Sharp corporation, Japan
pp. 517
Yu Chen, UCLA Department of Computer Science, Los Angeles, CA
Andrew B. Kahng, UCLA Department of Computer Science, Los Angeles, CA
Gabriel Robins, University of Virginia, Charlottesville
Alexander Zelikovsky, Georgia State University, Atlanta
pp. 523
Makoto Furuie, Osaka University, Japan
Bao-Yu Song, Osaka University, Japan
Yukihiro Yoshida, Osaka University, Japan
Takao Onoye, Kyoto University, Japan
Isao Shirakawa, Osaka University, Japan
pp. 529
Session E6: Analysis Techniques for Analog Circuits
M. M. Gourary, IPPM, Russian Academy of Sciences, Moscow
S. G. Rusakov, IPPM, Russian Academy of Sciences, Moscow
S. L. Ulyanov, IPPM, Russian Academy of Sciences, Moscow
M. M. Zharov, IPPM, Russian Academy of Sciences, Moscow
K. K. Gullapalli, Motorola, Austin, TX
B. J. Mulvaney, Motorola, Austin, TX
pp. 537
Tomohiro Fujita, Kyoto University, Japan
Ken-ichi Okada, Kyoto University, Japan
Hiroaki Fujita, Kyoto University, Japan
Hidetoshi Onodera, Kyoto University, Japan
Keikichi Tamaru, Kyoto University, Japan
pp. 547
Session A7: Advanced Design Techniques for Deep-Submicron System-On-A-Chip
Session B7 (Special Session): Future of System Level Design Languages
SystemC Standard (Abstract)
Guido Arnout, CoWare, Inc., Santa Clara, CA
pp. 573
Tommy Kuhn, University of T?bingen, Germany
Wolfgang Rosenstiel, University of T?bingen and FZI, Germany
pp. 579
Peter L. Flake, Co-Design Automation, Inc., San Jose, CA
Simon J. Davidmann, Co-Design Automation, Inc., San Jose, CA
pp. 583
Session C7: Delay Testing and Design-For-Testability
Jing-Jia Liou, University of California, Santa Barbara
Angela Krstic, University of California, Santa Barbara
Kwang-Ting Cheng, University of California, Santa Barbara
Deb Aditya Mukherjee, Intel Corporation
Sandip Kundu, Intel Corporation
pp. 587
Huan-Chih Tsai, University of California, Santa Barbara
Kwang-Ting Cheng, University of California, Santa Barbara
Vishwani D. Agrawal, Lucent Technologies, Murray Hill, NJ
pp. 593
Satoshi Ohtake, Nara Institute of Science and Technology, Japan
Hiroki Wada, Nara Institute of Science and Technology, Japan
Toshimitsu Masuzawa, Nara Institute of Science and Technology, Japan
Hideo Fujiwara, Nara Institute of Science and Technology, Japan
pp. 599
Jiun-Lang Huang, University of California, Santa Barbara
Kwang-Ting Cheng, University of California, Santa Barbara
pp. 605
Session D7 (Panel Discussion): Industry-Academia Cooperation
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Session E7: Signal Integrity / Noise Issues in Deep-Submicron
Young-Deuk Jeon, Sogang University, Seoul, Korea
Byeong-Lyeol Jeon, Hyundai Electronics Industries Co., Ltd., Ichon, Korea
Seung-Chul Lee, Sogang University, Seoul, Korea
Sang-Min Yoo, Sogang University, Seoul, Korea
Seung-Hoon Lee, Sogang University, Seoul, Korea
pp. 613
Edoardo Charbon, Cadence Design Systems, San Jose, CA
Luis Miguel Silveira, Instituto de Engenharia de Sistemas e Computadores, Lisboa, Portual
Paolo Miliozzi, Conxant Systems Inc., Newport Beach, CA
pp. 617
Session A8: High Speed LSI Design for Entertainment Application
Haruyuki Tago, Toshiba Corporation, Kawasaki, Japan
Kazuhiro Hashimoto, Toshiba Corporation, Kawasaki, Japan
Nobuyuki Ikumi, Toshiba Corporation, Kawasaki, Japan
Masato Nagamatsu, Toshiba Corporation, Kawasaki, Japan
Masakazu Suzuoki, Sony Computer Entertainment Inc., Tokyo, Japan
Yasuyuki Yamamoto, Sony Computer Entertainment Inc., Tokyo, Japan
pp. 631
Takayuki Kamei, TOSHIBA Corp., Japan
Hideki Takeda, TOSHIBA Corp., Japan
Yukio Ootaguro, TOSHIBA Corp., Japan
Takayoshi Shimazawa, TOSHIBA Corp., Japan
Kazuhiko Tachibana, TOSHIBA Corp., Japan
Shin'ichi Kawakami, Toshiba Microelectoronics Corp., Japan
Seiji Norimatsu, TOSHIBA Corp., Japan
Fujio Ishihara, TOSHIBA Corp., Japan
Toshinori Sato, TOSHIBA Corp., Japan
Hiroaki Murakami, TOSHIBA Corp., Japan
Nobuhiro Ide, TOSHIBA Corp., Japan
Yukio Endo, TOSHIBA Corp., Japan
Akira Aono, Toshiba Microelectoronics Corp., Japan
Atsushi Kunimatsu, TOSHIBA Corp., Japan
pp. 635
Norman Kojima, Toshiba Corporation Semiconductor Company, Japan
Yukiko Parameswar, Toshiba America Elec. Components, Inc., San Jose, CA
Christian Klingner, Toshiba America Elec. Components, Inc., San Jose, CA
Yukio Ohtaguro, Toshiba Corporation Semiconductor Company, Japan
Masataka Matsui, Toshiba Corporation Semiconductor Company, Japan
Shigeaki Iwasa, Toshiba Corporation Semiconductor Company, Japan
Tatsuo Teruyama, Toshiba Corporation Semiconductor Company, Japan
Takayoshi Shimazawa, Toshiba Corporation Semiconductor Company, Japan
Hideki Takeda, Toshiba Corporation Semiconductor Company, Japan
Kouji Hashizume, Toshiba Microelectronics Corp. Japan
Haruyuki Tago, Toshiba Corporation Semiconductor Company, Japan
Masaaki Yamada, Toshiba Corporation Semiconductor Company, Japan
pp. 641
Fujio Ishihara, Toshiba Corporation, Japan
Christian Klingner, Toshiba America Elec. Components, Inc., San Jose, CA
Ken-ichi Agawa, Toshiba Corporation, Japan
pp. 647
Session B8 (Panel Discussion): One Language or More? (How Can We Design an SoC at a System Level?)
Session D8: High Performance Partitioning
Yu-Liang Wu, The Chinese University of HK, Shatin
Xiao-Long Yuan, The Northwest Polytechnical University, China
David Ihsin Cheng, Ultima Interconnect Technology, Sunnyvale, CA
pp. 655
Andrew E. Caldwell, UCLA Computer Science Dept., Los Angeles, CA
Andrew B. Kahng, UCLA Computer Science Dept., Los Angeles, CA
Igor L. Markov, UCLA Computer Science Dept., Los Angeles, CA
pp. 661
Maogang Wang, Northwestern University, Evanston, IL
Sung Kyu Lim, UCLA, Los Angeles, CA
Jason Cong, UCLA, Los Angeles, CA
Majid Sarrafzadeh, Northwestern University, Evanston, IL
pp. 667
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