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Asia and South Pacific Design Automation Conference 2000 (ASP-DAC'00)
Yokohama, Japan
January 25-January 28
ISBN: 0-7803-5973-9
Shin'ichi Wakabayashi, Hiroshima University, Japan
Tetsushi Koide, The University of Tokyo, Japan
Naoyoshi Toshine, Hiroshima University, Japan
Masataka Yamane, Hiroshima University, Japan
Hajime Ueno, Hiroshima University, Japan
We have developed a new GA hardware called GAA-I (Genetic Algorithm Accelerator-I), in which the crossover operator to be applied to each individual was dynamically selected during the algorithm execution. GAA-I has some restrictions due to the limited chip size. In this paper, we extend the GAA-I and propose a new GA hardware, GAA-II, so that large, complex optimization problems can be solved. Furthermore, GAA-II has capability of parallel processing with other GAA-II chips. The GAA-II chip has been fabricated as a CMOS standard cell chip with 0.6 μm technology.
Citation:
Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Masataka Yamane, Hajime Ueno, "Genetic Algorithm Accelerator GAA-II," asp-dac, pp.9, Asia and South Pacific Design Automation Conference 2000 (ASP-DAC'00), 2000
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