- A
- ASP-DAC
- 1999
- Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99)
| | This Publication | | | | | | | |
| | | | Bibliographic References | | | |
| | | | |
Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99) Wanchai, Hong Kong January 18-January 21 ISBN: 0-7803-5012-X Table of Contents
 | null |
 | Session 1: Keynote Speech 1 |
 | Session 2A: Analog CAD |
Rong Luo, Tsinghua Univ., Beijing, P.R. China
Hui Wang, Tsinghua Univ., Beijing, P.R. China pp. 9
 | Session 2B: Physical Design 1 - Floorplanning |
 | Session 2C: Design Contest |
Yong Jee, Sogang University, Seoul, Korea pp. 25
Kang-Jin Lee, Hyundai Electronics Industries Co., Ltd., Ichon, Korea pp. 29
Dong-Wook Lee, Kwang-Ju Institute of Science and Technology(K-JIST)
Dong-Ik Lee, Kwang-Ju Institute of Science and Technology(K-JIST) pp. 33
Li Jiang, Tokyo Institute of Technology, Tokyo
Dongju Li, Tokyo Institute of Technology, Tokyo pp. 41
 | Session 3A: Circuit Simulation 1 |
Omar Wing, The Chinese University of Hong Kong, P. R. China pp. 61
M. M. Zharov, IPPM, Russian Academy of Sciences, Moscow, Russia pp. 65
 | Session 3B: Physical Design 2 - Partitioning |
Wen-Wei Lin, National Tsing Hua University, HsinChu, Taiwan pp. 77
 | Session 3C: EDA Roadmap |
 | Session 4A: Circuit Simulation 2 |
Zheng Hui, Tsinghua University, Beijing, P R. China
Tian Lilin, Tsinghua University, Beijing, P R. China pp. 89
 | Session 4B: Physical Design 3 - Interconnection |
Shihliang Ou, University of Southern California, Los Angeles pp. 105
Chi-Ying Tsui, HK University of Science and Technology, Kowloon, Hong Kong
Qing Wu, University of Southern California, Los Angeles pp. 109
 | Session 5A: Keynote Speech 2 |
 | Session 6A: Circuit 1 - Low-power/High-speed |
Yoshinori Gotoh, NTT Integrated Information & Energy System Laboratories, Japan
Shinsuke Konaka, NTT Integrated Information & Energy System Laboratories, Japan pp. 113
 | Session 6B: Physical Design 4 - Analog, Noise |
Tong Xiao, University of California, Santa Barbara pp. 137
Wai-chee Wong, The Hone Kong University of Science and Technology
Wai-on Law, Motorola Semiconductors Hong Kong Ltd. pp. 141
 | Session 6C: DA for Electronic Packages |
 | Session 6D: Poster Session |
Hoon Choi, Korea Advanced Institute of Science and Technology, Taejon, Korea
Hansoo Kim, Korea Advanced Institute of Science and Technology, Taejon, Korea
In-Cheol Park, Korea Advanced Institute of Science and Technology, Taejon, Korea
Seung Ho Hwang, Korea Advanced Institute of Science and Technology, Taejon, Korea
Chong-Min Kyung, Korea Advanced Institute of Science and Technology, Taejon, Korea pp. 157
M. M. Zharov, IPPM, Russian Academy of Sciences, Moscow, Russia pp. 165
Ren-Der Chen, National Cheng Kung University, Tainan, Taiwan
Jer Min Jou, National Cheng Kung University, Tainan, Taiwan pp. 185
Hui-Ru Jiang, National Chiao Tung University, Hsinchu, Taiwan pp. 189
 | Session 7A: Circuit 2 - Multmedia chip designs |
P. W. Cheng, The Hong Kong University of Science and Technology
H. C. Huang, The Hong Kong University of Science and Technology pp. 197
 | Session 7B: Physical Design 5 - Special Topics |
Anish Singh, University of Virginia, Charlottesville, VA pp. 221
 | Session 7C: Panel - System-on-a-chip |
 | Session 8A: Timing analysis |
Chi-ying Tsui, The Hong Kong University of Science & Technology, Clear Water Bay pp. 233
Payam Rabiei, University of Southern California, Los Angeles pp. 237
 | Session 8B: Physical Design 6 - Placement & Route |
Yici Cai, Tsinghua University, Beijing, China pp. 249
 | Session 9: Keynote Speech 3 |
 | Session 10A: Circuit 3 - Analog & Mixed Circuit |
Jack L. Chan, National Chiao Tung University, Taiwan; AMIC Technology, Taiwan pp. 261
 | Session 10B: Testing 1 |
Chi-Feng Wu, National Tsing Hua University, Hsinchu, Taiwan
Cheng-Wen Wu, National Tsing Hua University, Hsinchu, Taiwan pp. 279
Jian Xu, Fudan University, Shanghai, China pp. 283
 | Session 11A: Power Estimation/Low-power |
Yibin Ye, Purdue University, West Lafayette, IN pp. 299
 | Session 11B: Testing 2 - Testing and formal Verification |
Chun-Keung Lo, The Hong Kong University of Science and Technology pp. 307
Jin Ding, Beijing Univ. of Posts & Telecom., China
Yu-Liang Wu, The Chinese University of Hong Kong, Shatin pp. 311
 | Session 11C: Panel - VLSI Design Education |
 | Session 12A: BDD |
 | Session 12B: Systems/HW SW co-design |
 | Session 12C: Behavioral/FPGA |
Hongxi Xue, Tsinghua University, Beijing, P.R. China pp. 363 Usage of this product signifies your acceptance of the Terms of Use.
| | | | | | | |