In this paper, we introduce a high-speed and low power Phase-Frequency Detector (PFD) that is designed using modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop. This PFD has a simpler structure with using only 19 transistors. The operation range of this PFD is over 1.2Ghz without additional prescaler circuits. Furthermore, the PFD has a dead zone less than 0.01ns in the phase characteristics and has low phase sensitivity errors. The phase and frequency error detection range is not limited as in the case of the pt-type and nc-type PFDs. Also, the PFD is independent from the duty cycle of input signals. A new charge-pump circuit is presented that is designed using a charge-amplifier. A stand - by current enhances the speed of charge - pump and removes the charge - sharing which causes a phase noise in the charge - pump PLL. Also, the effects of clock feed - through are reduced by separating the output stage from UP and down signal. The simulation results base on a third - order PLL are presented to verify the lock - in process with the proposed PFD and Charge - pump circuits. The PFD and charge - pump circuits are designed using 0.8 ?m CMOS technology with 5V supply voltage.