Interconnect Delay Estimation Models for Synthesis and Design Planning

Jason Cong; David Zhigang Pan

doi:10.1109/ASPDAC.1999.759720

A
ASP-DAC
1999
Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99)
Abstract - Interconnect Delay Estimation Models for Synthesis and Design Planning

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Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99)

Interconnect Delay Estimation Models for Synthesis and Design Planning

Wanchai, Hong Kong

January 18-January 21

ISBN: 0-7803-5012-X

	ASCII Text	x
	Jason Cong, David Zhigang Pan, "Interconnect Delay Estimation Models for Synthesis and Design Planning," Asia and South Pacific Design Automation Conference, pp. 97, Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99), 1999.

	BibTex	x
	@article{ 10.1109/ASPDAC.1999.759720, author = {Jason Cong and David Zhigang Pan}, title = {Interconnect Delay Estimation Models for Synthesis and Design Planning}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {1999}, isbn = {0-7803-5012-X}, pages = {97}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.759720}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - Interconnect Delay Estimation Models for Synthesis and Design Planning SN - 0-7803-5012-X SP EP A1 - Jason Cong, A1 - David Zhigang Pan, PY - 1999 KW - null VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

Jason Cong, University of California, Los Angeles

David Zhigang Pan, University of California, Los Angeles

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.759720

In this paper we develop a set of interconnect delay estimation models with consideration of various layout optimizations, including optimal wire-sizing (OWS), simultaneous driver and wire sizing (SDWS), and simultaneous buffer insertion/sizing and wire sizing (BISWS). These models have been tested on a wide range of parameters and shown to have about 90% accuracy on average compared with those from running complex optimization algorithms directly followed by HSPICE simulations. Moreover, our models run in constant time in practice. As a result, these simple, fast, yet accurate models are expected to be very useful for a wide variety of purposes, including layout-driven logic and high level synthesis, performance-driven floorplanning, and interconnect planning.

Citation:

Jason Cong, David Zhigang Pan, "Interconnect Delay Estimation Models for Synthesis and Design Planning," asp-dac, pp.97, Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99), 1999

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