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Samos, Greece
July 23, 2005 to July 25, 2005
ISBN: 0-7695-2407-9
pp: 198-203
Yang Yang , Computer Science & Technology Dept. Tsinghua Univ. Beijing, P. R. China
Tong Jing , Computer Science & Technology Dept. Tsinghua Univ. Beijing, P. R. China
Xianlong Hong , Computer Science & Technology Dept. Tsinghua Univ. Beijing, P. R. China
Yu Hu , Computer Science & Technology Dept. Tsinghua Univ. Beijing, P. R. China
Qi Zhu , EECS Dept. UC at Berkeley U. S. A.
Xiaodong Hu , Inst Applied Math CAS Beijing, P. R. China
Guiying Yan , Inst Applied Math CAS Beijing, P. R. China
ABSTRACT
<p>CAD tools have become more and more important for integrated circuit (IC) design since a complicated system can be designed into a single chip, called system-on-a-chip (SOC), in which physical design tool is an essential and critical part. We try to consider the via minimization problem as early as possible in physical design. We propose a routing method focusing on minimizing vias while considering routability and wire-length constraint. That is, in the global routing phase, we minimize the number of bends, which is closely related to the number of vias. Previous work only dealt with very small nets, but our algorithm is general for the nets with any size. Experimental results show that our algorithm can greatly reduce the count of bends for various sizes of nets while meeting the constraints of congestion and wire-length.</p>
INDEX TERMS
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CITATION
Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu, Guiying Yan, "Via-Aware Global Routing for Good VLSI Manufacturability and High Yield", ASAP, 2005, 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors 2005, pp. 198-203, doi:10.1109/ASAP.2005.67
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