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| Samarjit Chakraborty, "Towards a Framework for System-Level Design of Multiprocessor SoC Platforms for Media Processing," 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors, pp. 65-72, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05), 2005. | |||
| BibTex | x | ||
| @article{ 10.1109/ASAP.2005.63, author = {Samarjit Chakraborty}, title = {Towards a Framework for System-Level Design of Multiprocessor SoC Platforms for Media Processing}, journal ={2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors}, volume = {0}, year = {2005}, issn = {1063-6862}, pages = {65-72}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.2005.63}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors TI - Towards a Framework for System-Level Design of Multiprocessor SoC Platforms for Media Processing SN - 1063-6862 SP65 EP72 A1 - Samarjit Chakraborty, PY - 2005 KW - null VL - 0 JA - 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors ER - | |||
Recently a number of "event-centric" models have been proposed for analyzing multimedia applications running on multiprocessor System-on-Chip (SoC) platforms. This has given shape to a general framework using which different timing and performance analysis questions can be answered in a single coherent manner. Central to this framework is a model for expressing the timing properties associated with different multimedia streams and a means for computing how these properties change as a stream gets successively processed by the different processors of a platform. In contrast to standard event models like periodic or sporadic, this model can accurately capture the datadependent execution time variabilities associated multimedia tasks and the burstiness of on-chip traffic resulting from multimedia processing. In this paper we give a high-level view of this framework, describe setups which currently can be modelled using it, and identify possible directions in which this framework should be extended to make it more usable.
