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12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00)
A 108 Gbps, 1.5 GHz 1D-DCT Architecture
Boston, Massachusetts
July 10-July 12
ISBN: 0-7695-0716-6
| ASCII Text | x | ||
| Ahmed Shams, Magdy Bayoumi, "A 108 Gbps, 1.5 GHz 1D-DCT Architecture," 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors, pp. 163, 12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00), 2000. | |||
| BibTex | x | ||
| @article{ 10.1109/ASAP.2000.862387, author = {Ahmed Shams and Magdy Bayoumi}, title = {A 108 Gbps, 1.5 GHz 1D-DCT Architecture}, journal ={2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors}, volume = {0}, year = {2000}, issn = {1063-6862}, pages = {163}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.2000.862387}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors TI - A 108 Gbps, 1.5 GHz 1D-DCT Architecture SN - 1063-6862 SP EP A1 - Ahmed Shams, A1 - Magdy Bayoumi, PY - 2000 VL - 0 JA - 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors ER - | |||
A high-performance 1D-DCT architecture is proposed. It is based on the New Distributed Arithmetic Architecture algorithm (NEDA) [1]. Enhancements to NEDA are proposed to reduce the number of computations. Only addition operations are used, with 42 additions to compute the outputs for an 8x1 DCT. No subtractions, multiplications, or ROM is needed. High-throughput is achieved by pipelining the architecture. In every clock cycle, it receives eight pixels (each is 9-bits) as inputs, and produces eight DCT coefficients (each is 14-bits). The delay of one pipeline stage is the delay of a 3-level 4:2 compressor tree. The architecture is implemented in 0.35? technologies; it runs at 1.5 GHz, and processes 108 Gbps of image/video sequence data.
Citation:
Ahmed Shams, Magdy Bayoumi, "A 108 Gbps, 1.5 GHz 1D-DCT Architecture," asap, pp.163, 12th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'00), 2000
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