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1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96)
Chicago, IL
August 19-August 23
ISBN: 0-8186-7542-X
Table of Contents
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Miscellaneous Applications, Chair: Jean-Michel Muller
K.P. Acken, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
H.N. Kim, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 3
V.E. Taylor, Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
J. Chen, Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
T. Canfield, Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
R. Stevens, Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
pp. 12
Jeffrey D. Hirschberg, hirsch@cse.ucsc.edu
Richard Hughey, rph@cse.ucsc.edu
Kevin Karplus, karplus@cse.ucsc.edu
Don Speck, University of California, Santa Cruz, CA 95064
pp. 25
H. Lim, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
C. Yim, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander, Jr., Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 35
Arithmetic Algorithms and Architectures, Chair: Luigi Dadda
J.-C. Bajard, Univ. de Provence, Marseille, France
L.-S. Didier, Univ. de Provence, Marseille, France
J.-M. Muller, Univ. de Provence, Marseille, France
pp. 45
J. Villalba, Dept. Comput. Archit., Malaga Univ., Spain
J.C. Arrabal, Dept. Comput. Archit., Malaga Univ., Spain
E.L. Zapata, Dept. Comput. Archit., Malaga Univ., Spain
E. Antelo, Dept. Comput. Archit., Malaga Univ., Spain
J.D. Bruguera, Dept. Comput. Archit., Malaga Univ., Spain
pp. 55
K.P. Acken, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
A.K. Garga, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 65
L. Song, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
K.K. Parhi, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 72
Plenary Session
Keynote Address
High Performance Multimedia Signal Processing - Is There a Future for DSP?
DSP Architectures, Chair: Arup Gupta
David A. Parker, Department of Electrical Engineering University of Minnesota
Keshab K. Parhi, Department of Electrical Engineering University of Minnesota
pp. 93
H. Yeo, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Y.H. Hu, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 122
Systolic Algorithms and Architectures, Chair: S.Y. Kung
Jurgen Teich, Institute TIK ETH Zurich, Gloriastrasse 35 CH-8092 Zurich, Switzerland
Lothar Thiele, Institute TIK ETH Zurich, Gloriastrasse 35 CH-8092 Zurich, Switzerland
Li Zhang, Institute TIK ETH Zurich, Gloriastrasse 35 CH-8092 Zurich, Switzerland
pp. 131
Hyuk-Jae Lee, Purdue University {hyuk,fortes}@ecn.purdue.edu
Jose A.B. Fortes, Purdue University {hyuk,fortes}@ecn.purdue.edu
pp. 155
M. Boo, Univ. Santiago de Compostela elmboo@usc.es
F. Arguello, Univ. Santiago de Compostela elmboo@usc.es
J.D. Bruguera, Univ. Santiago de Compostela elmboo@usc.es
E.L. Zapata, Univ. Santiago de Compostela elmboo@usc.es
pp. 165
Poster Session, Chair: Roger Woods
S. Peng, Aizu Univ., Fukushima, Japan
S. Sedukhin, Aizu Univ., Fukushima, Japan
I. Sedukhin, Aizu Univ., Fukushima, Japan
pp. 183
M. Vishwanath, Comput. Sci. Lab., Xerox Palo Alto Res. Center, CA, USA
R.M. Owens, Comput. Sci. Lab., Xerox Palo Alto Res. Center, CA, USA
pp. 193
G. Even, Fachbereich Inf., Saarlandes Univ., Saarbrucken, Germany
A. Litman, Fachbereich Inf., Saarlandes Univ., Saarbrucken, Germany
pp. 199
M.I. Patel, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
N. Ranganathan, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
pp. 221
A. Wang, Electrical Engineering Dept. UCLA, Los Angeles, CA 90095-1594
K. Yao, Electrical Engineering Dept. UCLA, Los Angeles, CA 90095-1594
R.E. Hudson, Electrical Engineering Dept. UCLA, Los Angeles, CA 90095-1594
D. Korompis, Electrical Engineering Dept. UCLA, Los Angeles, CA 90095-1594
F. Lorenzelli, Electrical Engineering Dept. UCLA, Los Angeles, CA 90095-1594
S. Soli, House Ear Institute Los Angeles,CA 90057
S. Gao, House Ear Institute Los Angeles,CA 90057
pp. 231
Daping Song, Centre de Recherche en Automatique de Nancy Universite de Nancy I, BP239, 54506 Vandoeuvre-les-Nancy cedex, France
Thierry Divoux, Centre de Recherche en Automatique de Nancy Universite de Nancy I, BP239, 54506 Vandoeuvre-les-Nancy cedex, France
Francis LePage, Centre de Recherche en Automatique de Nancy Universite de Nancy I, BP239, 54506 Vandoeuvre-les-Nancy cedex, France
pp. 250
Panel
High Speed Networks
Design Methodologies, Chair: Tobias G. Nell
R.W. Hartenstein, Kaiserslautern Univ., Germany
J. Becker, Kaiserslautern Univ., Germany
M. Herz, Kaiserslautern Univ., Germany
R. Kress, Kaiserslautern Univ., Germany
U. Nageldinger, Kaiserslautern Univ., Germany
pp. 274
D.R. Smith, Dept. of Comput. Sci., State Univ. of New York, Stony Brook, NY, USA
pp. 284
Rapid Prototyping, Chair: Robert Owens
Naren Narasimhan, University of Cincinnati
Vinoo Srinivasan, University of Cincinnati
Madhavi Vootukuru, University of Cincinnati
Jeff Walrath, University of Cincinnati
Sriram Govindarajan, University of Cincinnati
Ranga Vemuri, University of Cincinnati
pp. 303
H.W. Van Dijk, Philips Components, Eindhoven, Netherlands
G.J. Hekstra, Philips Components, Eindhoven, Netherlands
E.F. Deprettere, Philips Components, Eindhoven, Netherlands
pp. 323
Compilers I, Chair: Kung Yao
S. S. Bhattacharyya, Semiconductor Research Laboratory, Hitachi America, Ltd. shuvra@halsrl.com
S. Sriram, DSP R&D Center, Texas Instruments Incorporated sriram@hc.ti.com
E. A. Lee, University of California at Berkeley eal@eecs.berkeley.edu, fax: (510)642-2739.
pp. 365
Compilers II, Chair: Sayfe Kiaei
Edin Hodzic, HaL Computer Systems ehodzic@scu.edu
Weijia Shang, Santa Clara University wshang@scus19.scu.edu
pp. 402
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