CSDL - Proceedings A

Message from the Program Chairs (PDF)

pp. x

Program Committee (PDF)

pp. xi

Opening Session, Chair: P. Cappello

Keynote Address: Array Processing in Embedded Systems

Session 1: Scheduling and Mapping, Chair: J. Teich

The naive execution of affine recurrence equations (Abstract)

D. Wilde, Dept. of Comput. Sci., Oregon State Univ., Corvallis, OR, USA

S. Rajopadhye, Dept. of Comput. Sci., Oregon State Univ., Corvallis, OR, USA

pp. 1

PDF

Revisiting the Decomposition of Karp, Miller and Winograd (Abstract)

Alain Darte, Ecole Normale Sup_rieure de Lyon

Fredric Vivien, Ecole Normale Sup_rieure de Lyon

pp. 13

PDF

A Processor-Time-Minimal Schedule for 3D Rectilinear Mesh Algorithms (Abstract)

Chris Scheiman, University of California Santa Barbara

Peter Cappello, University of California Santa Barbara

pp. 26

PDF

Data Alignments for Modular Time-Space Mappings of BLAS-like Algorithms (Abstract)

Hyuk-Jae Lee, Purdue University, W. Lafayette, IN 47907

Jose A.B. Fortes, Purdue University, W. Lafayette, IN 47907

pp. 34

PDF

Session 2: Architectures I, Chair: C. Mongenet

Time-optimal ranking algorithms on sorted matrices (Abstract)

V. Bokka, Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA

H. Gurla, Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA

S. Olariu, Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA

J.L. Schwing, Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA

L. Wilson, Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA

pp. 42

PDF

Recomputing by Operand Exchanging: A Time-redundancy Approach for Fault-tolerant Neural Networks (Abstract)

Yuang-Ming Hsu, The University of Texas at Austin

Earl E. Swartzlander Jr, The University of Texas at Austin

Vincenzo Piuri, Politecnico di Milano

pp. 54

PDF

Design and Implementation of a Parallel Image Processor Chip for a SIMD Array Processor (Abstract)

Myung H. Sunwoo, Ajou University

Soohwan Ong, Ajou University

Byungdug Ahn, Ajou University

Kyungwoo Lee, Ajou University

pp. 66

PDF

A Scalable Halftoning Coprocessor Architecture (Abstract)

Anders Kugler, Swiss Federal Institute of Technology

Roger-David Hersch, Swiss Federal Institute of Technology

pp. 76

PDF

Horizontal Microcode Compaction for Programmable Systolic Accelerators (Abstract)

Paolo Ienne, Microcomputing Laboratory & Centre MANTRA

pp. 85

PDF

Session 3: Arithmetic I, Chair: R. Owens

Column Compression Pipelined Multipliers (Abstract)

Luca Breveglieri, Politecnico di Milano

Luigi Dadda, Politecnico di Milano

Vincenzo Piuri, Politecnico di Milano

pp. 93

PDF

A Processor for Staggered Interval Arithmetic (Abstract)

Michael J. Schulte, The University of Texas at Austin

Earl E. Swartzlander, Jr., The University of Texas at Austin

pp. 104

PDF

A simple array processor for binary prefix sums (Abstract)

Rong Lin, Dept. of Comput. Sci., State Univ. of New York, Genesco, NY, USA

S. Olariu, Dept. of Comput. Sci., State Univ. of New York, Genesco, NY, USA

pp. 113

PDF

Session 4: Poster Presentations, Chair: R. Owens

Parallel Digital Elevation Model Algorithm

The MGAP's programming environment and the *C++ language (Abstract)

R.S. Bajwa, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

R.M. Owens, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

M.J. Irwin, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

pp. 121

PDF

The VLSI design and implementation of the array processors of a multilayer vision system architecture (Abstract)

B. Saha, Dept. of Electr. Eng., Binghamton Univ., NY, USA

J.S. Mertoguno, Dept. of Electr. Eng., Binghamton Univ., NY, USA

N.G. Bourbakis, Dept. of Electr. Eng., Binghamton Univ., NY, USA

pp. 125

PDF

A Parallelizing Compilation Method for the Map-oriented Machine (Abstract)

Reiner W. Hartenstein, University of Kaiserslautern

Jrgen Becker, University of Kaiserslautern

Rainer Kress, University of Kaiserslautern

Helmut Reinig, University of Kaiserslautern

Karin Schmidt, University of Kaiserslautern

pp. 129

PDF

VLSI Algorithms for Compressed Pattern Search Using Tree Based Codes (Abstract)

Amar Mukherjee, University of Central Florida

Tinku Acharya, University of Maryland

pp. 133

PDF

Parallel Sequence Comparison and Alignment (Abstract)

Richard Hughey, University of California, Santa Cruz (UCSC)

pp. 137

PDF

The Systolic Design of a Block Regularised Parameter Estimator using Hierarchical Signal Flow Graphs (Abstract)

D.W. Brown, The Queen's University of Belfast

F.M.F. Gaston, The Queen's University of Belfast

pp. 141

PDF

Invited Talk, Chair: S.Y. Kung

Real-Time Image Processing for Multimedia Applications at Matra-Hachette

Session 5: Signal and Image Processing, Chair: S. Y. Kung

Systolic Filter for Fast DNA Similarity Search (Abstract)

Pascale Guerdoux-Jamet, IRISA

Dominique Lavenier, IRISA

pp. 145

PDF

A Solid Translation Engine using Ray Representation (Abstract)

Thomas Alexander, Duke University

John L. Ellis, Duke University

Gershon Kedem, Duke University

pp. 157

PDF

Input buffering requirements of a Systolic Array for the Inverse Discrete Wavelet Transform (Abstract)

Robert Lang, University of Newcastle

Andrew Spray, University of Newcastle

pp. 166

PDF

Synthesis of VLSI Architectures for Two-Dimensional Discrete Wavelet Transforms (Abstract)

Jongwoo Bae, University of Southern California

Viktor K. Prasanna, University of Southern California

pp. 174

PDF

Session 6: Motion Estimation, Chair: P. Quinton

Parallel Implementation of the Full Search Block Matching Algorithm for Motion Estimation (Abstract)

P. Baglietto, DIST - University of Genoa

M. Maresca, DIST - University of Genoa

A. Migliaro, DIST - University of Genoa

M. Migliardi, DIST - University of Genoa

pp. 182

PDF

MOVIE: A Building Block for the Design of Real Time Simulator of Moving Pictures Compression Algorithms (Abstract)

Ronan Barzic, CCETT

Christian Bouville, CCETT

Francois Charot, IRISA,Campus de Beaulieu

Gwendal Le Fol, IRISA,Campus de Beaulieu

Pascal Lemonnier, IRISA,Campus de Beaulieu

Charles Wagner, IRISA,Campus de Beaulieu

pp. 193

PDF

Motion Estimation Algorithms on Fine Grain Array Processor (Abstract)

Heung-Nam Kim, The Pennsylvania State University

Mary Jane Irwin, The Pennsylvania State University

Robert Michael Owens, The Pennsylvania State University

pp. 204

PDF

Bit Level Block Matching Systolic Arrays (Abstract)

Yin Chan, Princeton University

S. Y. Kung, Princeton University

pp. 214

PDF

Invited Talk, Chair: J.M. Muller

Computer Arithmetic: Exploiting Redundancy in Number Representations

Session 7: Architecture II, Chair: J.M. Muller

Techniques for Yield Enhancement of VLSI Adders (Abstract)

Zhan Chen, University of Massachusetts

Israel Koren, University of Massachusetts

pp. 222

PDF

Interfacing FPGA/VLSI Processor Arrays (Abstract)

Joseph Fernando, Wright State University

Jack Jean, Wright State University

pp. 230

PDF

Implementation of Parallel Arithmetic in a Cellular Automaton (Abstract)

Richard Squier, Georgetown University

Ken Steiglitz, Princeton University

Mariusz Jakubowski, Princeton University

pp. 238

PDF

Session 8: Arithmetic II, Chair: E.E. Swartzlander

Digit On-line Large Radix CORDIC Rotator (Abstract)

Roberto R. Osorio, University of Santiago de Compostela

Elisardo Antelo, University of Santiago de Compostela

Javier D. Bruguera, University of Santiago de Compostela

Julio Villalba, University of Malaga

Emilio L. Zapata, University of Malaga

pp. 246

PDF

CORDIC Architectures with Parallel Compensation of the Scale Factor (Abstract)

J. Villalba, University of Malaga, SPAIN

J.A. Hidalgo, University of Malaga, SPAIN

E.L. Zapata, University of Malaga, SPAIN

E. Antelo, University of Santiago de Compostela, SPAIN

J.D. Bruguera, University of Santiago de Compostela, SPAIN

pp. 258

PDF

An array processor for inner product computations using a Fermat number ALU (Abstract)

W. Luo, VLSI Res. Group, Windsor Univ., Ont., Canada

G.A. Jullien, VLSI Res. Group, Windsor Univ., Ont., Canada

N.M. Wigley, VLSI Res. Group, Windsor Univ., Ont., Canada

W.C. Miller, VLSI Res. Group, Windsor Univ., Ont., Canada

Z. Wang, VLSI Res. Group, Windsor Univ., Ont., Canada

pp. 270

PDF

Design of a systolic coprocessor for rational addition (Abstract)

T. Jebelean, RISC-Linz, Austria

pp. 282

PDF

Multilayer Cellular Algorithm for Complex Number Multiplication (Abstract)

V.P. Markova, Computing Center, Siberian Div. of the Russian Academy of Sciences

pp. 290

PDF

Session 9: Design Methodologies, Chair: J. Fortes

Minimizing Synchronization Overhead in Statically Scheduled Multiprocessor Systems (Abstract)

Shuvra S. Bhattacharyya, Hitachi America Ltd.

Sundararajan Sriram, University of California, Berkeley California, 94720

Edward A. Lee, University of California, Berkeley California, 94720

pp. 298

PDF

Synthesis of Multirate VLSI Arrays (Abstract)

P. Lenders

S. Rajopadhye

pp. 310

PDF

A Design Tool for the Specification and the Simulation of Array Processors Architectures -- Application to Image Processing: The Extraction of Regions of Interests (Abstract)

G. Ramstein, SEI, IRESTE, Cedex, France

O. Deforges, SEI, IRESTE, Cedex, France

P. Bakowski, SEI, IRESTE, Cedex, France

pp. 322

PDF

Precise Tiling for Uniform Loop Nests (Abstract)

Pierre-Yves Calland, Ecole Nationale Superieure de Lyon

Tanguy Risset, IRISA, Campus de Beaulieu

pp. 330

PDF

Closing Session and Best Paper Award, Chair: J. Fortes

Index of Authors (PDF)

pp. 339