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2001 Conference on Advanced Research in VLSI (ARVLSI'01)
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy
Salt Lake City, Utah
March 14-March 16
ISBN: 0-7695-1038-8
| ASCII Text | x | ||
| Seongmoo Heo, Ronny Krashinsky, Krste Asanovic, "Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy," Advanced Research in VLSI, Conference on, pp. 59, 2001 Conference on Advanced Research in VLSI (ARVLSI'01), 2001. | |||
| BibTex | x | ||
| @article{ 10.1109/ARVLSI.2001.915551, author = {Seongmoo Heo and Ronny Krashinsky and Krste Asanovic}, title = {Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy}, journal ={Advanced Research in VLSI, Conference on}, volume = {0}, year = {2001}, isbn = {0-7695-1038-8}, pages = {59}, doi = {http://doi.ieeecomputersociety.org/10.1109/ARVLSI.2001.915551}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Advanced Research in VLSI, Conference on TI - Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy SN - 0-7695-1038-8 SP EP A1 - Seongmoo Heo, A1 - Ronny Krashinsky, A1 - Krste Asanovic, PY - 2001 VL - 0 JA - Advanced Research in VLSI, Conference on ER - | |||
This work presents new techniques to evaluate the energy and delay of flip-flop and latch designs and shows that no single existing design performs well across the wide range of operating regimes present in complex systems. We propose the use of a selection of flip-flop and latch designs, each tuned for different activation patterns and speed requirements. We illustrate the use of our technique on a pipelined MIPS processor datapath running SPECint95 benchmarks, where we reduce total flip-flop and latch energy by over 60% without increasing cycle time.
Citation:
Seongmoo Heo, Ronny Krashinsky, Krste Asanovic, "Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy," arvlsi, pp.59, 2001 Conference on Advanced Research in VLSI (ARVLSI'01), 2001
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