CSDL - Proceedings A

Acknowledgments (PDF)

pp. ix

Committees (PDF)

pp. x

Invited Speaker

Silicon Adventures-Go Ahead; Be Bold! (Abstract)

Charles L. Seitz, Myricom, Inc.

pp. 2

PDF

Architectural Considerations for Application-Specific Counterflow Pipelines (Abstract)

Bruce R. Childers, University of Virginia

Jack W. Davidson, University of Virginia

pp. 3

PDF

Architecture Design of Reconfigurable Pipelined Datapaths (Abstract)

Darren C. Cronquist, University of Washington

Chris Fisher, University of Washington

Miguel Figueroa, University of Washington

Paul Franklin, University of Washington

Carl Ebeling, University of Washington

pp. 23

PDF

Session 2: VLSI Focal Plane Architectures

A Column-based Processing Array for High-speed Digital Image Processing (Abstract)

Tonia Morris, Intel Corporation

Erica Fletcher, Intel Corporation

Cyrus Afghahi, Intel Corporation

Sami Issa, Intel Corporation

Kevin Connolly, Intel Corporation

Jean-Charles Korta, Intel Corporation

pp. 42

PDF

Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel Processor (Abstract)

Sek M. Chai, Georgia Institute of Technology

Antonio Gentile, Georgia Institute of Technology

D. Scott Wills, Georgia Institute of Technology

pp. 57

PDF

A Throughput-On-Demand Address-Event Transmitter for Neuromorphic Chips (Abstract)

Kwabena Boahen, University of Pennsylvania

pp. 72

PDF

XXI Century Gigascale Integration (GSI) : The Interconnect Problem (Abstract)

James D. Meindl, Georgia Institute of Technology

pp. 88

PDF

Area-Universal Circuits with Constant Slowdown (Abstract)

Sandeep N. Bhatt, Bell Communications Research

Gianfranco Bilardi, Universita' di Padova and University of Illinois at Chicago

Geppino Pucci, Universita' di Padova

pp. 89

PDF

A Quantitative Approach to Nonlinear Process Design Rule Scaling (Abstract)

Spencer M. Gold, University of Michigan

Richard B. Brown, University of Michigan

Bruce Bernhardt, Motorola, Inc.

pp. 99

PDF

Session 4: VLSI Modeling and Technology

Interconnect-Dominated VLSI Design (Abstract)

P. Ghosh, Rensselaer Polytechnic Institute

R. Mangaser, Rensselaer Polytechnic Institute

C. Mark, Rensselaer Polytechnic Institute

K. Rose, Rensselaer Polytechnic Institute

pp. 114

PDF

Noise Margin Constraints for Interconnectivity in Deep Submicron Low Power and Mixed-Signal VLSI Circuits (Abstract)

Li-Rong Zheng, Royal Institute of Technology

Hannu Tenhunen, Royal Institute of Technology

pp. 123

PDF

Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing (Abstract)

Nestoras Tzartzanis, University of Southern California

William C. Athas, University of Southern California

pp. 137

PDF

System-on-a-Chip VLSI - Is It Finally Really Here? (Abstract)

Robert W. Brodersen, University of California at Berkeley

pp. 154

PDF

Algorithms Promoting the Use of Dual Supply Voltages for Power-Driven Designs (Abstract)

Chingwei Yeh, National Chung-Cheng University

Min-Cheng Chang, National Chung-Cheng University

Yin-Shuin Kang, National Chung-Cheng University

pp. 155

PDF

Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution (Abstract)

Vijay Sundararajan, University of Minnesota

Keshab K. Parhi, University of Minnesota

pp. 170

PDF

Translinear Analog Signal Processing: A Modular Approach to Large-Scale Analog Computation with Multiple-Input Translinear Elements (Abstract)

Session 6: VLSI Circuits

Bradley A. Minch, Cornell University

pp. 186

PDF

Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines (Abstract)

Ayoob E. Dooply, University of California at San Diego

Kenneth Y. Yun, University of California at San Diego

pp. 200

PDF

Adaptive Circuits Using pFET Floating-Gate Devices (Abstract)

Paul Hasler, Georgia Institute of Technology

Bradley A. Minch, Cornell University

Chris Diorio, University of Washington

pp. 215

PDF

VLSI Architecture: Past, Present, and Future (Abstract)

William J. Dally, Stanford University

Steve Lacy, Stanford University

pp. 232

PDF

Exploring Microprocessor Architectures for Gigascale Integration (Abstract)

Lucian Codrescu, Georgia Institute of Technology

Mondira Deb-Pant, Georgia Institute of Technology

Tarek Taha, Georgia Institute of Technology

John Eble, Georgia Institute of Technology

Scott Wills, Georgia Institute of Technology

James Meindl, Georgia Institute of Technology

pp. 242

PDF

The Ultrascalar Processor-An Asymptotically Scalable Superscalar Microarchitecture (Abstract)

Dana S. Henry, Yale University

Bradley C. Kuszmaul, Yale University

Vinod Viswanath, Yale University

pp. 256

PDF

Session 8: Vision Processing Chips

Conjunction Search Using a 1-D, Analog VLSI-based, Attentional Search/Tracking Chip (Abstract)

Timothy Horiuchi, Johns Hopkins University

Ernst Niebur, Johns Hopkins University

pp. 276

PDF

A Two-Dimensional, Object-Based Analog VLSI Visual Attention System (Abstract)

Charles S. Wilson, Georgia Institute of Technology

Tonia G. Morris, Georgia Institute of Technology

Stephen P. DeWeerth, Georgia Institute of Technology

pp. 291

PDF

Multi-Chip Neuromorphic Motion Processing (Abstract)

Charles M. Higgins, California Institute of Technology

Christof Koch, California Institute of Technology

pp. 309

PDF

Problems and Prospects for Electrical Signaling (Abstract)

John Poulton, University of North Carolina at Chapel Hill

pp. 326

PDF

Compact Fault Dictionary Construction for Efficient Isolation of Faults in Analog and Mixed-Signal Circuits (Abstract)

Sudip Chakrabarti, Georgia Institute of Technology.

Abhijit Chatterjee, Georgia Institute of Technology.

pp. 327

PDF

Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and Test (Abstract)

Ramakrishna Voorakaranam, Georgia Institute of Technology

Abhijit Chatterjee, Georgia Institute of Technology

pp. 342

PDF

Who Put the Sugar in Sydney Harbor? (Abstract)

Neil Weste, Macquarie University

pp. 358

PDF

Battery-powered, Wireless MEMS Sensors for High-Sensitivity Chemical and Biological Sensing (Abstract)

C.L. Britton Jr, Oak Ridge National Laboratory and The University of Tennessee

R.J. Warmack, Oak Ridge National Laboratory and The University of Tennessee

S.F. Smith, Oak Ridge National Laboratory and The University of Tennessee

A.L. Wintenberg, Oak Ridge National Laboratory and The University of Tennessee

T. Thundat, Oak Ridge National Laboratory

G.M. Brown, Oak Ridge National Laboratory

W.L. Bryan, Oak Ridge National Laboratory

J.C. Depriest, Oak Ridge National Laboratory

M.N. Ericson, Oak Ridge National Laboratory

M.S. Emery, Oak Ridge National Laboratory

M.R. Moore, Oak Ridge National Laboratory

G.W. Turner, Oak Ridge National Laboratory

L.G. Clonts, Oak Ridge National Laboratory

R.L. Jones, The University of Tennessee

T.D. Threatt, The University of Tennessee

Z. Hu, The University of Tennessee

J.M. Rochelle, The University of Tennessee

pp. 359

PDF

MEMS-Based Capacitor Arrays for Programmable Interconnect and RF Applications (Abstract)

B.E. Duewer, North Carolina State University

J.M. Wilson, North Carolina State University

D.A. Winick, North Carolina State University

P.D. Franzon, North Carolina State University

pp. 369

PDF

Author Index (PDF)

pp. 378