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2009 19th IEEE Symposium on Computer Arithmetic
Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units
Portland, Oregon, USA
June 08-June 10
ISBN: 978-0-7695-3670-5
| ASCII Text | x | ||
| Jochen Preiss, Maarten Boersma, Silvia Melitta Mueller, "Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units," Computer Arithmetic, IEEE Symposium on, pp. 48-56, 2009 19th IEEE Symposium on Computer Arithmetic, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/ARITH.2009.17, author = {Jochen Preiss and Maarten Boersma and Silvia Melitta Mueller}, title = {Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units}, journal ={Computer Arithmetic, IEEE Symposium on}, volume = {0}, year = {2009}, issn = {1063-6889}, pages = {48-56}, doi = {http://doi.ieeecomputersociety.org/10.1109/ARITH.2009.17}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Computer Arithmetic, IEEE Symposium on TI - Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units SN - 1063-6889 SP48 EP56 A1 - Jochen Preiss, A1 - Maarten Boersma, A1 - Silvia Melitta Mueller, PY - 2009 KW - clockgating KW - power reduction KW - fused multiply-add KW - floating-point hardware KW - IEEE 754 Standard VL - 0 JA - Computer Arithmetic, IEEE Symposium on ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ARITH.2009.17
The paper introduces fine-grain clockgating schemes for fused multiply-add-type floating-point units (FPU). The clockgating is based on instruction type, precision and operand values. The presented schemes focus on reducing the power at peak performance, where each FPU stage is used in nearly every cycle and conventional schemes have little impact on the power consumption. Depending on the instruction mix, the schemes allow to turn off 18% to 74%of the register bits. Even for the worst case instruction 18% to 37% of the FPU are shut down depending on the data patterns.
Index Terms:
clockgating, power reduction, fused multiply-add, floating-point hardware, IEEE 754 Standard
Citation:
Jochen Preiss, Maarten Boersma, Silvia Melitta Mueller, "Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units," arith, pp.48-56, 2009 19th IEEE Symposium on Computer Arithmetic, 2009
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