CSDL - Proceedings A

Dedication (PDF)

pp. ix

Committees (PDF)

pp. x

Additional Reviewers (PDF)

pp. xii

Session 1: Keynote Talk

Computer Arithmetic — An Algorithm Engineer?s Perspective (PDF)

David W. Matula, Southern Methodist University

pp. 2

Session 2: Multiplication

High-Performance Left-to-Right Array Multiplier Design (Abstract)

Zhijun Huang, University of California at Los Angeles

Miloš D. Ercegovac, University of California at Los Angeles

pp. 4

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Multiple-Precision Fixed-Point Vector Multiply-Accumulator Using Shared Segmentation (Abstract)

Dimitri Tan, Motorola Inc.

Albert Danysh, Motorola Inc.

Michael Liebelt, University of Adelaide

pp. 12

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Some Optimizations of Hardware Multiplication by Constant Matrices (Abstract)

Nicolas Boullis, École Normale Supérieure de Lyon

Arnaud Tisserand, École Normale Supérieure de Lyon

pp. 20

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A Less Recursive Variant of Karatsuba-Ofman Algorithm for Multiplying Operands of Size a Power of Two (Abstract)

Serdar S. Erdem, Gebze Yüksek Teknoloji Enstitüsü

Çetin K. Koç, Oregon State University

pp. 28

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Session 3: Division

Revisiting SRT Quotient Digit Selection (Abstract)

Peter Kornerup, University of Southern Denmark

pp. 38

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SRT Division Algorithms as Dynamical Systems (Abstract)

Mark McCann, University of British Columbia

Nicholas Pippenger, University of British Columbia

pp. 46

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A New Iterative Structure for Hardware Division: The Parallel Paths Algorithm (Abstract)

Eric Rice, University of California at Santa Cruz

Richard Hughey, University of California at Santa Cruz

pp. 54

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Prescaled Integer Division (Abstract)

David W. Matula, Southern Methodist University

Alex Fit-Florea, Southern Methodist University

pp. 63

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Session 4: Floating Point

Hardware Implementations of Denormalized Numbers (Abstract)

Eric M. Schwarz, IBM Server Division

Martin Schmookler, IBM Server Division

Son Dao Trong, IBM Server Division

pp. 70

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Representable Correcting Terms for Possibly Underflowing Floating Point Operations (Abstract)

Sylvie Boldo, Laboratoire de l?Informatique du Parall?lisme

Marc Daumas, Laboratoire de l?Informatique du Parall?lisme

pp. 79

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High Performance Floating-Point Unit with 116 Bit Wide Divider (Abstract)

Guenter Gerwig, IBM Server Division

Holger Wetter, IBM Server Division

Eric M. Schwarz, IBM Server Division

Juergen Haess, IBM Server Division

pp. 87

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The Case for a Redundant Format in Floating Point Arithmetic (Abstract)

Hossam A. H. Fahmy, Stanford University

Michael J. Flynn, Stanford University

pp. 95

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Session 5: Decimal Arithmetic and Revisions to the IEEE 754 Standard

Decimal Floating-Point: Algorism for Computers (Abstract)

Michael F. Cowlishaw, IBM UK Ltd. and University of Warwick

pp. 104

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Panel: Revisions to the IEEE 754 Standard for Floating-Point Arithmetic (PDF)

Eric Schwarz, IBM Corporation

pp. 112

Session 6: Elementary Functions

"Partially Rounded" Small-Order Approximations for Accurate, Hardware-Oriented, Table-Based Methods (Abstract)

Jean-Michel Muller, Ecole Normale Supérieure de Lyon

pp. 114

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An Overview of Floating-Point Support and Math Library on the Intel® XScale™ Architecture (Abstract)

Cristina Iordache, Intel Corporation

Ping Tak Peter Tang, Intel Corporation

pp. 122

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Theorems on Efficient Argument Reductions (Abstract)

Ren-Cang Li, University of Kentucky

Sylvie Boldo, Laboratoire de léInformatique du Parallélisme

Marc Daumas, Laboratoire de léInformatique du Parallélisme

pp. 129

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Accelerating Sine and Cosine Evaluation with Compiler Assistance (Abstract)

Peter Markstein, Hewlett-Packard Laboratories

pp. 137

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Session 7: Testing and Error Analysis

Worst Cases and Lattice Reduction (Abstract)

Damien Stehlé, ENS Paris

Vincent Lefèvre, Technopôle de Nancy-Brabois

Paul Zimmermann, Technopôle de Nancy-Brabois

pp. 142

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Isolating Critical Cases for Reciprocals Using Integer Factorization (Abstract)

John Harrison, Intel Corporation

pp. 148

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Solving Range Constraints for Binary Floating-Point Instructions (Abstract)

Abraham Ziv, IBM Research Labs

Merav Aharoni, IBM Research Labs

Sigal Asaf, IBM Research Labs

pp. 158

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A Parametric Error Analysis of Goldschmidt?s Division Algorithm (Abstract)

Guy Even, Tel-Aviv University

Peter-Michael Seidel, Southern Methodist University

Warren E. Ferguson

pp. 165

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Session 8: Cryptography

A Unidirectional Bit Serial Systolic Architecture for Double-Basis Division over GF(2^m) (Abstract)

Amir K. Daneshbeh, University of Waterloo

M. A. Hasan, University of Waterloo

pp. 174

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Efficient Multiplication in GF(p^k) for Elliptic Curve Cryptography

Low Complexity Sequential Normal Basis Multipliers over GF(2^m) (Abstract)

Arash Reyhani-Masoleh, University of Waterloo

M. Anwar Hasan, University of Waterloo

pp. 188

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A Low Complexity and a Low Latency Bit Parallel Systolic Multiplier over GF(2^m) Using an Optimal Normal Basis of Type II (Abstract)

Soonhak Kwon, Sungkyunkwan University

pp. 196

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Session 9: Powering, Multiplication, and Counters

High-Radix Iterative Algorithm for Powering Computation (Abstract)

J.-A. Piñeiro, Universidad Santiago de Compostela, Spain

M. D. Ercegovac, University of California at Los Angeles

J. D. Bruguera, Universidad Santiago de Compostela, Spain

pp. 204

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On-Line Multiplication in Real and Complex Base (Abstract)

Christiane Frougny, LIAFA, CNRS UMR and Université Paris 8

Athasit Surarerks, Chulalongkorn University

pp. 212

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A VLSI Algorithm for Modular Multiplication/Division (Abstract)

Marcelo E. Kaihara, Nagoya University

Naofumi Takagi, Nagoya University

pp. 220

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Saturating Counters: Application and Design Alternatives (Abstract)

Israel Koren, University of Massachusetts at Amherst

Yaron Koren, Bear Stearns

Bejoy G. Oomman, Genesys Testware

pp. 228

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Session 10: Number Systems

Error-Free Arithmetic for Discrete Wavelet Transforms Using Algebraic Integers (Abstract)

K. A. Wahid, University of Calgary

V. S. Dimitrov, University of Calgary

G. A. Jullien, University of Calgary

pp. 238

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On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge (Abstract)

Sorin Cotofana, Delft University of Technology

Casper Lageweg, Delft University of Technology

Stamatis Vassiliadis, Delft University of Technology

pp. 245

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The Interval Logarithmic Number System (Abstract)

Mark G. Arnold, Lehigh University

Jesus Garcia, Lehigh University

Michael J. Schulte, University of Wisconsin-Madison

pp. 253

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Scaling an RNS Number Using the Core Function (Abstract)

Neil Burgess, Cardiff University

pp. 262

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Session 11: Modeling and Design of Arithmetic Components

Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders (Abstract)

Vojin G. Oklobdzija, University of California at Davis

Bart R. Zeydel, University of California at Davis

Hoang Dao, University of California at Davis

Sanu Mathew, Intel Corporation

Ram Krishnamurthy, Intel Corporation

pp. 272

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Tutorial: Design of Power Efficient VLSI Arithmetic: Speed and Power Trade-Offs (PDF)

Vojin G. Oklobdzija, University of California at Davis

Ram Krishnamurthy, Intel Corporation

pp. 280

Author Index

Author Index (PDF)

pp. 281