Abstract: This paper presents the application of the Linear Sequential Array (LSA) organization to on-line division. The LSA method was originally developed for conventional digit-recurrence algorithms, but in this paper we apply it to the on-line division algorithm. The resulting architecture is a modular and fast pipelined structure which, due to a constant fanout, make the critical path delay, and consequently the clock cycle time, less sensitive to operand's precision. Such approach is particularly suitable for FPGA implementation for its modularity and reduced fanout. The basics of on-line division is presented, followed by the derivation of data dependencies and architecture according to the LSA design methodology. Experimental data is provided for both the LSA on-line divider design and standard on- line design, using 0.5_m CMOS ASIC and FPGA technologies.