CSDL - Proceedings A

Symposium Committee (PDF)

pp. ix

Program Committee (PDF)

pp. x

List of Reviewers (PDF)

pp. xi

Invited Talk, Chair: Israel Koren

Computer Arithmetic - A Programmer's Perspective (PDF)

Richard P. Brent, Oxford University

pp. 2

Processor Enhancements, Chair: Peter Kornerup

New Algorithms for Improved Transcendental Functions on IA-64 (Abstract)

Shane Story, Intel Corporation

Ping Tak, Intel Corporation

Peter Tang, Intel Corporation

pp. 4

PDF

A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector Extension (Abstract)

C. Roth

J. Lent

pp. 12

PDF

Addition, Chair: Neil Weste

Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition (Abstract)

Dhananjay S. Phatak, State University of New York at Binghamton

I. Koren, University of Massachusetts

pp. 22

PDF

A Family of Adders (Abstract)

S. Knowles

pp. 30

PDF

Reduced Latency IEEE Floating-Point Standard Adder Architectures (Abstract)

A. Beaumont-Smith, The University of Adelaide

N. Burgess, The University of Adelaide

S. Lefrere, The University of Adelaide

C.C. Lim, The University of Adelaide

pp. 35

PDF

Division, Chair: Renato Stefanelli

On the Design of High-Radix On-Line Division for Long Precision (Abstract)

Alexandre F. Tenca, Oregon State University

Milos D. Ercegovac, University of California at Los Angeles

pp. 44

PDF

Boosting Very-High Radix Division with Prescaling and Selection by Rounding (Abstract)

Paolo Montuschi, Politecnico di Torino

Tomas Lang, University of California at Irvine

pp. 52

PDF

Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16 (Abstract)

Alberto Nannarelli, University of California at Irvine

Tomas Lang, University of California at Irvine

pp. 60

PDF

Cryptography and Graphics, Chair: Milos Ercegovac

Montgomery Modular Exponentiation on Reconfigurable Hardware (Abstract)

Thomas Blum, Worcester Polytechnic Institute

pp. 70

PDF

Moduli for Testing Implementations of the RSA Cryptosystem (Abstract)

Colin D. Walter, U.M.I.S.T.,

pp. 78

PDF

Digit-Recurrence Algorithm for Computing Euclidean Norm of a 3-D Vector (Abstract)

Naofumi Takagi, Nagoya University

Seiji Kuwahara, Nagoya University

pp. 86

PDF

Divide and Square Root, Chair: Atsuki Inoue

Correctness Proofs Outline for Newton-Raphson Based Floating-Point Divide and Square Root Algorithms (Abstract)

Marius A. Cornea-Hasegan, Intel Corporation

Roger A. Golliver, Intel Corporation

Peter Markstein, Hewlett-Packard

pp. 96

PDF

Floating Point Division and Square Root Algorithms and Implementation in the AMD-K7 Microprocessor (Abstract)

Stuart F. Oberman

pp. 106

PDF

Series Approximation Methods for Divide and Square Root in the Power3(TM) Processor (Abstract)

Martin S Schmookler, IBM Corporation

Ramesh C. Agarwal, IBM Corporation

Fred G. Gustavson, IBM Corporation

pp. 116

PDF

High-Speed Inverse Square Roots (Abstract)

Michael J. Schulte, Lehigh University

Kent E. Wires, Lehigh University

pp. 124

PDF

Number Systems, Chair: Colin Walter

Arithmetic with Signed Analog Digits (Abstract)

A. Saed

M. Ahmadi

G.A. Jullien

pp. 134

PDF

A 32-Bit Logarithmic Arithmetic Unit and its Performance Compared to Floating-Point (Abstract)

J.N. Coleman

E.I. Chester

pp. 142

PDF

Necessary and Sufficient Conditions for Parallel, Constant Time Conversion and Addition (Abstract)

Peter Kornerup, Odense University

pp. 152

PDF

Residue Number Systems, Chair: Graham Jullien

Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication (Abstract)

Reto Zimmermann

pp. 158

PDF

A Reverse Converter for the 4-moduli Superset {2^n-1, 2^n, 2^n+1, 2^(n+1)+1} (Abstract)

pp. 168

PDF

VLSI Costs of Arithmetic Parallelism: A Residue Reverse Conversion Perspective (Abstract)

pp. 176

PDF

CORDIC Algorithms, Chair: Jeong Lee

Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm (Abstract)

J. Hormigo, University of Malaga

J. Villalba, University of Malaga

E.L. Zapata, University of Malaga

pp. 186

PDF

Complex Logarithmic Number System Arithmetic Using High-Radix Redundant CORDIC Algorithms (Abstract)

D. Lewis

pp. 194

PDF

Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding (Abstract)

pp. 204

PDF

Multiplication and Rounding, Chair: William McAllister

Area ? Delay (A T) Efficient Multiplier Based on an Intermediate Hybrid Signed-Digit (HSD-1) Representation (Abstract)

Jeng-Jong J. Lue, Summit Systems, Inc.

Dhananjay S. Phatak, State University of New York at Binghamton

pp. 216

PDF

A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication (Abstract)

Guy Even, Tel-Aviv University

Peter-M. Seidel, University of Saarland

pp. 225

PDF

On Infinitely Precise Rounding for Division, Square Root, Reciprocal and Square Root Reciprocal (Abstract)

Cristina Iordache, Southern Methodist University

David W. Matula, Southern Methodist University

pp. 233

PDF

Number-Theoretic Test Generation for Directed Rounding (Abstract)

Michael Parks, Sun Microsystems

pp. 241

PDF

Floating Point, Chair: Stuart F. Oberman

Multiplications of Floating Point Expansions (Abstract)

Marc Daumas

pp. 250

PDF

The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures (Abstract)

Eric M. Schwarz, IBM

Ronald M. Smith, IBM

Christopher A. Krygowski, IBM

pp. 258

PDF

Floating-Point Unit in Standard Cell Design with 116 Bit Wide Dataflow (Abstract)

Guenter Gerwig, IBM

Michael Kroener, IBM

pp. 266

PDF

Author Index (PDF)

pp. 274