CSDL - Proceedings A

Dedication (PDF)

pp. ix

Committees (PDF)

pp. x

Reviewers (PDF)

pp. xii

Session 1: Arithmetic Circuits, Chair: George Taylor

A Radix-8 CMOS S/390 Multiplier (Abstract)

Eric M. Schwarz, IBM

Robert M. Averill, III, IBM

Leon J. Sigal, IBM

pp. 2

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A GaAs 32-bit Adder (Abstract)

Andrew Beaumont-Smith, The University of Adelaide

Neil Burgess, The University of Adelaide

pp. 10

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SRT Division Architectures and Implementations (Abstract)

David L. Harris, Stanford University

Stuart F. Oberman, Stanford University

Mark A. Horowitz, Stanford University

pp. 18

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Power-Delay Characteristics of CMOS Multipliers (Abstract)

Thomas K. Callaway

Earl E. Swartzlander Jr

pp. 26

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Session 2: Number Systems, Chair: Israel Koren

On Radix Representation of Rings (Abstract)

Asger Munk Nielsen, Dept. of Math. & Comput. Sci., Odense Univ., Denmark

Peter Kornerup, Dept. of Math. & Comput. Sci., Odense Univ., Denmark

pp. 34

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Theory and applications for a double-base number system (Abstract)

V.S. Dimitrov, VLSI Res. Group, Windsor Univ., Canada

G.A. Jullien, VLSI Res. Group, Windsor Univ., Canada

W.C. Miller, VLSI Res. Group, Windsor Univ., Canada

pp. 44

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Session 3: Floating-Point Arithmetic - 1, Chair: William McAllister

On the Design of IEEE Compliant Floating Point Units (Abstract)

Guy Even, University des Saarlandes

Wolfgang Paul, University des Saarlandes

pp. 54

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A Priori Worst-Case Error Bounds for Floating-Point Computations (Abstract)

Walter Kramer, Universit?t Karlsruhe

pp. 64

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Session 4: Division, Reciprocation, Multiplication and Exponentiation, Chair: Milos Ercegovac

Multiprecision Division on an 8-bit Processor (Abstract)

Eric Rice, University of California, Santa Cruz

Richard Hughey, University of California, Santa Cruz

pp. 74

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Faithful Interpolation in Reciprocal Tables (Abstract)

Debjit Das Sarma, Texas Instruments

David W. Matula, Southern Methodist University

pp. 82

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Exponentiation using Division Chains (Abstract)

Colin D. Walter, Computation Department, U.M.I.S.T.

pp. 92

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Implementing Multiply-Accumulate Operation in Multiplication Time (Abstract)

Paul F. Stelling, California University of California, Davis, USA

Vojin G. Oklobdzija, California University of California, Davis, USA

pp. 99

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Session 5: Rotations and Elementary Functions - 1, Chair: Jeong-A Lee

CORDIC Vectoring with Arbitrary Target Value (Abstract)

Tomas Lang, University of California at Irvine

Elisardo Antelo, Universidade de Santiago de Compostela

pp. 108

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Fast Rotations: Low-cost Arithmetic Methods for Orthonormal Rotation (Abstract)

Gerben J. Hekstra, Delft University of Technology

Ed F.A. Deprettere, Delft University of Technology

pp. 116

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Generating a Power of an Operand by a Table Look-up and a Multiplication (Abstract)

Naofumi Takagi, Nagoya University

pp. 126

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Towards Correctly Rounded Transcendentals (Abstract)

Vincent Lefevre, Ecole Normale Superieure de Lyon

Arnaud Tisserand, Ecole Normale Superieure de Lyon

Jean-Michel Muller, CNRS

pp. 132

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Session 6: Floating-Point Arithmetic - 2, Chair: Ted Williams

Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder (Abstract)

David W. Matula, Southern Methodist University, Texas

Asger Munk Nielsen, Odense University, Denmark

pp. 140

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Pipelined Packet-Forwarding Floating Point: II. An Adder (Abstract)

Asger Munk Nielsen, Odense University, Denmark

David W. Matula, Southern Methodist University, Texas

C. N. Lyu, Southern Methodist University, Texas

Guy Event, Univ. des Saarlandes, Germany

pp. 148

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The SNAP Project: Design of Floating Point Arithmetic Units (Abstract)

Stuart F. Oberman, Stanford University

Hesham Al-Twaijry, Stanford University

Michael J. Flynn, Stanford University

pp. 156

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Session 7: Elementary Functions - 2, Chair: Dan Zuras

Fast Table-Driven Algorithms for Interval Elementary Functions (Abstract)

Douglas M. Priest, Sun Microsystems, Inc.

pp. 168

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Symmetric Bipartite Tables for Accurate Function Approximation (Abstract)

Michael J. Schulte, Lehigh University

James E. Stine, Lehigh University

pp. 175

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High-Performance Hardware for Function Generation (Abstract)

Jun Cao, San Jose State University

Belle Wei, San Jose State University

pp. 184

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Session 8: Complex Arithmetic, Chair: Renato Stefanelli

Arithmetic Co-transformations in the Real and Complex Logarithmic Number Systems (Abstract)

Mark G. Arnold, University of Wyoming

Thomas A. Bailey, University of Wyoming

John R. Cowles, University of Wyoming

Mark D. Winkel, Somatogen, Inc.

pp. 190

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Real/Complex Reconfigurable Arithmetic Using Redundant Complex Number Systems (Abstract)

Takafumi Aoki, Tohoku University

Hiroaki Amada, Tohoku University

Tatsuo Higuchi, Tohoku University

pp. 200

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Algorithms for Multi-Exponentiation Based on Complex Arithmetic (Abstract)

V.S. Dimitrov, VLSI Res. Group, Windsor University, Canada

G.A. Jullien, VLSI Res. Group, Windsor University, Canada

W.C. Miller, VLSI Res. Group, Windsor University, Canada

pp. 208

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Session 9: Residue Number Systems, Finite Fields and Cryptography - 1, Chair: Luigi Dadda

Fraction-Free RNS Algorithms for Solving Linear Systems (Abstract)

Peter R Turner, US Naval Academy

pp. 218

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Fast Software Exponentiation in GF(2^k) (Abstract)

C. K. Koc, Oregon State University

T. Acar, Oregon State University

pp. 225

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Session 10: Residue Number Systems, Finite Fields and Cryptography - 2, Chair: Simon Knowles

An IWS Montgomery Modular Multiplication Algorithm (Abstract)

Jean-Claude Bajard, Universit? de Provence, France

Laurent-Stéphane Didier, Universit? de Provence, France

Peter Kornerup, University of Odense, Denmark

pp. 234

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Design and Implementation of An RNS Division Algorithmm (Abstract)

Ahmad A. Hiasat, Princess Sumaya University, JORDAN

Hoda S. Abdel-Aty-Zohdy, Oakland University, MI, USA

pp. 240

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Scaled and Unscaled Residue Number System to Binary Conversion Techniques using the Core Function (Abstract)

Neil Burgess, University of Adelaide

pp. 250

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Session 11: Miscellaneous, Chair: Peter Kornerup

On-the-Fly Algorithms and Sequential Machines (Abstract)

Christiane Frougny, L.I.A.F.A (L.I.T.P.)

pp. 260

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The Half-Adder Form and Early Branch Condition Resolution (Abstract)

David R. Lutz, Bell Laboratories

D. N. Jayasimha, Intel Corporation

pp. 266

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Synchronous Up/Down Counter with Clock Period Independent of Counter Size (Abstract)

Mircea R. Stan, University of Virginia

pp. 274

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A Q-Coder Algorithm with Carry Free Addition (Abstract)

Gianluca Cena, Politecnico di Torino

Paolo Montuschi, Politecnico di Torino

Luigi Ciminiera, Politecnico di Torino

Andrea Sanna, Politecnico di Torino

pp. 282

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Author Index (PDF)

pp. 291