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Vienna
April 18, 2006 to April 20, 2006
ISBN: 0-7695-2466-4
pp: 289-294
John Paul Walters , Wayne State University, Detroit, MI
Bashar Qudah , Wayne State University, Detroit, MI
Vipin Chaudhary , Wayne State University Detroit, MI
ABSTRACT
Due to the ever-increasing size of sequence databases it has become clear that faster techniques must be employed to effectively perform biological sequence analysis in a reasonable amount of time. Exploiting the inherent parallelism between sequences is a common strategy. In this paper we enhance both the fine-grained and coursegrained parallelism within the HMMER [2] sequence analysis suite. Our strategies are complementary to one another and, where necessary, can be used as drop-in replacements to the strategies already provided within HMMER. We use conventional processors (Intel Pentium IV Xeon) as well as the freely available MPICH parallel programming environment [1]. Our results show that the MPICH implementation greatly outperforms the PVM HMMER implementation, and our SSE2 implementation also lends greater computational power at no cost to the user.
INDEX TERMS
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CITATION
John Paul Walters, Bashar Qudah, Vipin Chaudhary, "Accelerating the HMMER Sequence Analysis Suite Using Conventional Processors", AINA, 2006, Proceedings. 20th International Conference on Advanced Information Networking and Applications, Proceedings. 20th International Conference on Advanced Information Networking and Applications 2006, pp. 289-294, doi:10.1109/AINA.2006.68
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