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ACSD
1998
First International Conference on Application of Concurrency to System Design (ACSD'98)
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First International Conference on Application of Concurrency to System Design (ACSD'98)
Fukushima, Japan
March 23-March 26
ISBN: 0-8186-8350-3
Table of Contents
Message from Chairs
(PDF)
pp. viii
ABSTRACT
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CSD'98 Organization
(PDF)
pp. x
ABSTRACT
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Program Committee
(PDF)
pp. xi
ABSTRACT
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List of Reviewers
(PDF)
pp. xii
ABSTRACT
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Tutorial Papers
Combining Structural and Symbolic Methods for the Verification of Concurrent Systems
(Abstract)
Jordi Cortadella
, Universitat Politecnica de Catalunya
pp. 2
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Logic and Functional Verification in a Commercial Semiconductor Environment
(Abstract)
Jainendra Kumar
, Advanced Systems Technology Lab, MOTOROLA Inc.
Carl Pixley
, Advanced Systems Technology Lab, MOTOROLA Inc.
pp. 8
ABSTRACT
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How to Make Concurrent Programs Highly Reliable- More than State Space Analysis
(Abstract)
Naoshi Uchihira
, Toshiba Corporation
pp. 16
ABSTRACT
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System-Level Design Models and Implementation Techniques
(Abstract)
Luciano Lavagno
, Dipartimento di Elettronica Politecnico di Torino
pp. 24
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Hierarchical Models
Hierarchical Concurrent Finite State Machines in Ptolemy
(Abstract)
Bilung Lee
, University of California at Berkeley
Edward A. Lee
, University of California at Berkeley
pp. 34
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Visual Formalisms Revisited
(Abstract)
R. Grosu
G. Stefanescu
M. Broy
realistic applications.
pp. 41
ABSTRACT
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A Translation of Statecharts into Signal Approach of Time, Interoperability
(Abstract)
J.R. Beauvais
, IRISA, Campus de Beaulieu
R. Houdebine
, IRISA, Campus de Beaulieu
P. Le Guernic
, IRISA, Campus de Beaulieu
E. Rutten
, IRISA, Campus de Beaulieu
T. Gautier
, IRISA, Campus de Beaulieu
pp. 52
ABSTRACT
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Hierarchical Verification
Verification of Parameterized Asynchronous Circuits: A Case Study
(Abstract)
Tomohiro Yoneda
, Tokyo Institute of Technology
Yutaka Ohtsuka
, Tokyo Institute of Technology
Mart Saarepera
, Tokyo Institute of Technology
pp. 64
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Unbounded Verification Results by Finite-State Compositional Techniques: 10^any States and Beyond
(Abstract)
Antti Valmari
, Tampere University of Technology
Ilkka Kokkarinen
, Tampere University of Technology
pp. 75
ABSTRACT
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Systems with Timing
Modeling and Verification of Biphase Mark Protocolsin Duration Calculus Using PVS
(Abstract)
Dang Van Hung
, The United Nations University
pp. 88
ABSTRACT
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Formal Verification of Real-Time Software by Symbolic Model-Checker
(Abstract)
Kazuhiro Nakamura
, Nara Institute of Science and Technology
Satoshi Yamane
, Nara Institute of Science and Technology
pp. 99
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Integrating the Verification of Timing, Performance and Correctness Properties of Concurrent Systems
(Abstract)
A. Cerone
, University of South Australia
D.A. Kearney
, University of South Australia
G. J. Milne
, University of South Australia
pp. 109
ABSTRACT
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Timing Extensions of STG Model and a Method to Simulate Timed STG Behavior in VHDL Environment
(Abstract)
Michael V. Goncharov
, Institute for Analytical Instrumentation of RAS
Alexander B. Smirnov
, Institute for Analytical Instrumentation of RAS
Nikolai A. Starodoubtsev
, Institute for Analytical Instrumentation of RAS
Ilya V. Klotchkov
, St.-Petersburg State University,
pp. 120
ABSTRACT
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PN-Based Verification
Efficient Approach to Symbolic State Exploration of Complex Parallel Controllers
(Abstract)
K. Bilinski
, Technical University of Zielona Gora
E.L. Dagless
, University of Bristol, UK
pp. 132
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Calculating Place Capacity for Petri Nets Using Unfoldings
(Abstract)
Toshiyuki Miyamoto
, Osaka University
Sadatoshi Kumagai
, Osaka University
pp. 143
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Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings
(Abstract)
Alex Kondratyev
Jordi Cortadella
Michael Kishinevsky
Luciano Lavagno
Alexander Taubin
Alex Yakovlev
pp. 152
ABSTRACT
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High-Level Nets
Using Object-Oriented Algebraic Nets for the Reverse Engineering of Java Programs: A Case Study
(Abstract)
Giovanna Di Marzo Serugendo
, CUI, University of Geneva
Nicolas Guelfi
, LGL-DI, Swiss Federal Institute of Technology
pp. 166
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Proving Correctness of Distributed Algorithms Using High-Level Petri Nets - A Case Study
(Abstract)
Jörg Desel
, Universit?t Karlsruhe
Ekkart Kindler
, Humboldt-Universit?t zu Berlin
pp. 177
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Verifying Fault Tolerance of Distributed Algorithms Formally - An Example
(Abstract)
Hagen Völzer
, Humboldt-Universitaet zu Berlin
pp. 187
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Hardware Verification
Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation
(Abstract)
Miroslav N. Velev
, Carnegie Mellon University
Randal E. Bryant
, Carnegie Mellon University
pp. 200
ABSTRACT
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Event-Driven Verification of Switch-Level Correctness Concerns
(Abstract)
Radu Negulescu
, University of Waterloo
pp. 213
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Panel Discussion
Hot Topics in System Design
Algebraic Models and Languages
A True Concurrency Semantics for ET-LOTOS
(Abstract)
Howard Bowman
, University of Kent
Joost-Pieter Katoen
, University of Erlangen-Nuernberg
pp. 228
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Recursive Nets in the Box Algebra
(Abstract)
Raymond Devillers
, Universite Libre de Bruxelles
Maciej Koutny
, University of Newcastle
pp. 239
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A Presentation of Regular Languages in the Assumption - Commitment Framework
(Abstract)
Swarup Mohalik
, The Institute of Mathematical Sciences
R. Ramanujam
, The Institute of Mathematical Sciences
pp. 250
ABSTRACT
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Case Studies
Modeling and Analyzing Interorganizational Workflows
(Abstract)
W.M.P. Van der Aalst
, Eindhoven University of Technology
pp. 262
ABSTRACT
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A Java-based Formal Development Environment for Factory Communication Systems
(Abstract)
Claudio Demartini
, Politecnico di Torino
Riccardo Sisto
, Politecnico di Torino
pp. 273
ABSTRACT
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Traffic Lights - An AutoFocus Case Study
(Abstract)
Franz Huber
, Technische Universit?t M?nchen
Sascha Molterer
, Technische Universit?t M?nchen
Bernhard Schätz
, Technische Universit?t M?nchen
Oscar Slotosch
, Technische Universit?t M?nchen
Alexander Vilbig
, Technische Universit?t M?nchen
pp. 282
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Author Index
(PDF)
pp. 295
ABSTRACT
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