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Formal Verification of a Pipelined Microprocessor
September/October 1990 (vol. 7 no. 5)
pp. 52-64

The application of modern functional languages and supporting verification technology to a scaled-down but realistic microprocessor is described. The model is of an infinite stream of machine instructions consuming an infinite stream of interrupt signals and is specified at two levels: instruction and hardware design. A correctness criterion is stated for an appropriate sense of equivalent behavior of these levels and proved using a mechanically supported induction argument. The functional-language-based verification system Clio and the Mini Cayuga microprocessor are described. The formal specification and verification process are examined in detail.

Index Terms:
pipelined microprocessor; modern functional languages; verification technology; infinite stream; machine instructions; interrupt signals; hardware design; correctness criterion; mechanically supported induction argument; functional-language-based verification system Clio; Mini Cayuga microprocessor; formal specification; verification process; functional programming; microprocessor chips; parallel architectures; parallel machines; program verification
Citation:
Mandayam Srivas, Mark Bickford, "Formal Verification of a Pipelined Microprocessor," IEEE Software, vol. 7, no. 5, pp. 52-64, Sept.-Oct. 1990, doi:10.1109/52.57892
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