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Reducing the Variance of Point-to-Point Transfers for Parallel Real-Time Programs
Winter 1994 (vol. 2 no. 4)
pp. 20-31
| ASCII Text | x | ||
| Ronald Mraz, "Reducing the Variance of Point-to-Point Transfers for Parallel Real-Time Programs," IEEE Concurrency, vol. 2, no. 4, pp. 20-31, Winter, 1994. | |||
| BibTex | x | ||
| @article{ 10.1109/88.345963, author = {Ronald Mraz}, title = {Reducing the Variance of Point-to-Point Transfers for Parallel Real-Time Programs}, journal ={IEEE Concurrency}, volume = {2}, number = {4}, issn = {1063-6552}, year = {1994}, pages = {20-31}, doi = {http://doi.ieeecomputersociety.org/10.1109/88.345963}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Concurrency TI - Reducing the Variance of Point-to-Point Transfers for Parallel Real-Time Programs IS - 4 SN - 1063-6552 SP20 EP31 EPD - 20-31 A1 - Ronald Mraz, PY - 1994 VL - 2 JA - IEEE Concurrency ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/88.345963
Investigations that analyze the time an operating system takes to schedule, interrupt and "context-switch" to another process or job have helped developers produce highly optimized and tuned operating systems that can provide more than 99% sustained processor use for most uniprocessor applications. However, when these operating systems are installed on CPUs that are interconnected with a low-latency (user-space) communication mechanism, large variances typically occur in the time it takes to send a point-to-point message. In this article, we examine how to reduce the difference between worst-case and average-case message latency that can contribute to variance in fine-grain parallel programs. Changing how the operating system handles interrupt processing and scheduling can greatly reduce the difference between these latencies, thus increasing a program's performance.
Citation:
Ronald Mraz, "Reducing the Variance of Point-to-Point Transfers for Parallel Real-Time Programs," IEEE Concurrency, vol. 2, no. 4, pp. 20-31, Winter 1994, doi:10.1109/88.345963
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