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Optimizing a Superscalar Machine to Run Vector Code
May 1993 (vol. 1 no. 2)
pp. 73-83
| ASCII Text | x | ||
| "Optimizing a Superscalar Machine to Run Vector Code," IEEE Concurrency, vol. 1, no. 2, pp. 73-83, May, 1993. | |||
| BibTex | x | ||
| @article{ 10.1109/MCC.1993.10008, author = {}, title = {Optimizing a Superscalar Machine to Run Vector Code}, journal ={IEEE Concurrency}, volume = {1}, number = {2}, issn = {1063-6552}, year = {1993}, pages = {73-83}, doi = {http://doi.ieeecomputersociety.org/10.1109/MCC.1993.10008}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Concurrency TI - Optimizing a Superscalar Machine to Run Vector Code IS - 2 SN - 1063-6552 SP73 EP83 EPD - 73-83 PY - 1993 VL - 1 JA - IEEE Concurrency ER - | |||
A streamlined vector architecture and the IBM superscalar RISC System/6000 are discussed. It is shown, step-by-step, how each handles the same program. The factors that let vector machines outperform the RS/6000 are identified. Several extensions to the RS/6000 architecture that could help it attain vector-level performance on code with long vectors are proposed.
Citation:
"Optimizing a Superscalar Machine to Run Vector Code," IEEE Concurrency, vol. 1, no. 2, pp. 73-83, May 1993, doi:10.1109/MCC.1993.10008
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