Francisco Cazorla , Barcelona SuperComputing Center, barcelona
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2014.59
Critical Real-Time Embedded Systems (CRTES), which are deployed among others in cars, planes and satellites, feature increasingly complex safety-related performance-demanding functionality. Such functionality can only realistically be provided by means of advanced (high-performance) hardware and software. This will inevitably shift CRTES from using simple control software running on in-order, single-core processors with no caches to complex multi-sensor and multi-actuator software running on &#x0060;aggressive' processors implemented in nanoscale technology deploying several computing cores and a cache hierarchy. However, the use of aggressive technologies and architectures challenges time predictability and reliability, which are mandatory features in CRTES. In this paper we present a processor design that reconciles all three goals, namely, predictability, reliability and high performance. Our design obtains trustworthy and tight worst-case execution time (WCET) estimates for safety-critical applications running on high-performance hardware facing hard and soft errors by means of a smart use of timing analysis techniques in combination with minor hardware modifications.
Francisco Cazorla, "Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments", IEEE Micro, , no. 1, pp. 1, PrePrints PrePrints, doi:10.1109/MM.2014.59