Hiroshi Nakamura , The University of Tokyo, Hongo
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2013.133
A scalable heterogeneous multi-core processor is developed. 3D heterogeneous chip stacking of a general-purpose CPU and reconfigurable multicore accelerators enables various trade-off between performance and energy consumption. The stacked chips interconnect through a scalable 3D Network on Chip (NoC). By simply changing the number of stacked accelerator chips, processor parallelism can be widely scaled. No design change is needed, and hence no additional Non-Recurring Engineering (NRE) cost is required. An inductive-coupling ThruChip Interface (TCI) is applied to stacked-chip communications, forming a low-cost and robust high-speed 3D NoC. A prototype system Cube-1 has been developed with 65nm CMOS test chips. Successful system operations including 10-hours continuous Linux OS operation are confirmed. Simple filters and a streaming application were implemented on Cube-1 and performance acceleration up to about three times was achieved.
Hiroshi Nakamura, "A Scalable 3D Heterogeneous Multi-Core Processor with Inductive-Coupling ThruChip Interface", IEEE Micro, , no. 1, pp. 1, PrePrints PrePrints, doi:10.1109/MM.2013.133