Hiroshi Okano , FUJITSU LABORATORIES LIMITED, kawasaki
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2013.135
Fujitsu has developed SPARC64TM X1,2, a new processor for UNIX servers that runs at a speed of 3 GHz and consists of 16 cores, a 24-Mbyte shared level-2 (L2) cache, memory controllers, IO controllers and system controllers for connecting multiple chips. We have enhanced the micro-architecture and introduced an extended instruction set called High Performance Computing-Arithmetic Computational Extensions3 (HPC-ACE), used previously in the K computer4. The peak memory bandwidth is 102 Gbytes per second. Extremely high throughput performance is realized by these features. In addition, we have added new functions to the processor core pipelines, which accelerate certain software tasks such as cryptographic processing. We call these functions 'software on chip' (SWoC). Furthermore, high reliability technology used in mainframes is employed to ensure stable operation of mission-critical systems. This article describes the past and current direction of the micro-architecture of the SPARC64TM processor series, gives an overview of SPARC64TM X, and presents results for the performance and power efficiency of SWoC.
Hiroshi Okano, "SPARC64 X: Fujitsu's New Generation 16-core Processor for UNIX Server", IEEE Micro, , no. 1, pp. 1, PrePrints PrePrints, doi:10.1109/MM.2013.135