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FT-Matrix: A Coordination-aware Architecture for Signal Processing
PrePrint
ISSN: 0272-1732
Shuming Chen, National University of Defense Technology, Chang Sha
Yaohua Wang, National University of Defense Technology, Chang Sha
Sheng Liu, National University of Defense Technology, Chang Sha
Jianghua Wan, National University of Defense Technology, Chang Sha
Haiyan Chen, National University of Defense Technology, Chang Sha
Hengzhu Liu, National University of Defense Technology, Chang Sha
Kai Zhang, National University of Defense Technology, Chang Sha
Xiangyuan Liu, National University of Defense Technology, Chang Sha
Xi Ning, National University of Defense Technology, Chang Sha
Vector-SIMD architectures have gained increasing attention due to their high performance in signal processing applications. However, the performance of existing vector-SIMD architectures is still limited due to their inefficiency in the coordinated exploitation of different hardware units. To solve this problem, this paper proposes the FT-Matrix architecture, which improves the coordination of traditional vector-SIMD architectures from three aspects: (1) the cooperation between scalar and SIMD unit is refined with the dynamic coupling execution scheme; (2) the communication among SIMD lanes is enhanced with the matrix-style communication; (3) data sharing among vector memory banks is accomplished by the unaligned vector memory accessing scheme. The evaluation result exhibits an average performance gain of 58.5% against vector-SIMD architectures without the proposed improvements. A four-core chip with each core built upon the FT-Matrix architecture is also under fabrication.
Citation:
Shuming Chen, Yaohua Wang, Sheng Liu, Jianghua Wan, Haiyan Chen, Hengzhu Liu, Kai Zhang, Xiangyuan Liu, Xi Ning, "FT-Matrix: A Coordination-aware Architecture for Signal Processing," IEEE Micro, 16 Dec. 2013. IEEE computer Society Digital Library. IEEE Computer Society, <http://doi.ieeecomputersociety.org/10.1109/MM.2013.129>
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