Aravindkumar Rajendiran , University of Waterloo, Waterloo
Hiren Patel , University of Waterloo, Waterloo
Sundaram Ananthanarayanan , Stanford University, Stanford
Mahesh Tripunitara , University of Waterloo, Waterloo
Dan Wang , University of Waterloo, Waterloo
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2013.130
This work presents a method to reliably perform computations in the presence of hard faults arising from aggressive technology scaling, and design defects from human error. Our method is based on the observation that a single Turing-complete instruction can mirror the semantics of any other instruction. One such instruction is the subleq instruction, which has been used for instructional purposes in the past. The scope for using such a Turing-complete instruction is far greater than that of instructional purposes, and thus, we present its applicability to fault tolerance. In particular, we extend a MIPS processor with a co-processor (called the ultra-reduced instruction set co-processor -- URISC) that implements the subleq instruction. The URISC executes sequences of subleq to mimic the semantics of instructions that are known to be faulty on the MIPS core after testing. We implement a new back-end for the LLVM compiler that generates the sequence of subleq for instructions marked as faulty. This presents a hardware-software approach to fault recovery. Our hardware prototype called MIPS-URISC synthesizes onto an Altera FPGA. We experimentally evaluate the following: impact of single-upset faults on the instruc- tions that are rendered faulty, the area overhead of the URISC, and the performance overhead of using subleq with the URISC.
Aravindkumar Rajendiran, Hiren Patel, Sundaram Ananthanarayanan, Mahesh Tripunitara, Dan Wang, "Reliable Computing with Ultra-Reduced Instruction Set Co-processors", IEEE Micro, , no. 1, pp. 1, PrePrints PrePrints, doi:10.1109/MM.2013.130