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Issue No.06 - Nov.-Dec. (2014 vol.34)
pp: 86-94
Dan Wang , University of Waterloo
Aravindkumar Rajendiran , University of Waterloo
Sundaram Ananthanarayanan , Stanford University
Hiren Patel , University of Waterloo
Mahesh V. Tripunitara , University of Waterloo
Siddharth Garg , New York University
This work presents a method to reliably perform computations in the presence of both hard faults arising from aggressive technology scaling and design defects from human error. The method is based on the observation that a single Turing-complete instruction can mirror any other instruction's semantics. One such instruction is the subleq instruction, which has been used for instructional purposes in the past. The scope of using such an instruction is far greater than that of instructional purposes, and thus, the authors present its applicability to fault tolerance. In particular, they extend a million-instructions-per-second (MIPS) processor with the ultra-reduced instruction set coprocessor (URISC), which implements the subleq instruction. They use the URISC to execute sequences of subleq to mimic the semantics of instructions that are known to be faulty on the MIPS core after testing. The LLVM compiler back end generates the sequence of subleq for instructions marked as faulty. This presents a hardware-software approach to fault recovery. The authors experimentally evaluate the impact of single-upset faults on the instructions that are rendered faulty, the area overhead of the URISC, and the performance overhead of using the URISC.
Registers, Instruction sets, Decoding, Network reliability, Multicore processing, Benchmark testing, Semantics,URISC, microprocessor reliability, hard faults, Turing-complete ISA, ultra-reduced instruction set coprocessor
Dan Wang, Aravindkumar Rajendiran, Sundaram Ananthanarayanan, Hiren Patel, Mahesh V. Tripunitara, Siddharth Garg, "Reliable Computing with Ultra-Reduced Instruction Set Coprocessors", IEEE Micro, vol.34, no. 6, pp. 86-94, Nov.-Dec. 2014, doi:10.1109/MM.2013.130
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