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Issue No.06 - Nov.-Dec. (2014 vol.34)
pp: 64-73
Shuming Chen , National University of Defense Technology, China
Yaohua Wang , National University of Defense Technology, China
Sheng Liu , National University of Defense Technology, China
Jianghua Wan , National University of Defense Technology, China
Haiyan Chen , National University of Defense Technology, China
Hengzhu Liu , National University of Defense Technology, China
Kai Zhang , National University of Defense Technology, China
Xiangyuan Liu , National University of Defense Technology, China
Xi Ning , National University of Defense Technology, China
ABSTRACT
Vector-SIMD architectures have gained increasing attention because of their high performance in signal-processing applications. However, the performance of existing vector-SIMD architectures remains limited because of their inefficiency in the coordinated exploitation of different hardware units. To solve this problem, this article proposes the FT-Matrix architecture, which improves the coordination of traditional vector-SIMD architectures from three aspects: the cooperation between the scalar and SIMD unit is refined with the dynamic coupling execution scheme, the communication among SIMD lanes is enhanced with the matrix-style communication, and data sharing among vector memory banks is accomplished by the unaligned vector memory accessing scheme. Evaluation results show an average performance gain of 58.5 percent against vector-SIMD architectures without the proposed improvements. A four-core chip with each core built on the FT-Matrix architecture is also under fabrication.
INDEX TERMS
Integrated circuits, Signal processing, Hardware, Registers, Memory management,SIMDU, vector-SIMD, coordination, scalar unit, SU, SIMD unit
CITATION
Shuming Chen, Yaohua Wang, Sheng Liu, Jianghua Wan, Haiyan Chen, Hengzhu Liu, Kai Zhang, Xiangyuan Liu, Xi Ning, "FT-Matrix: A Coordination-Aware Architecture for Signal Processing", IEEE Micro, vol.34, no. 6, pp. 64-73, Nov.-Dec. 2014, doi:10.1109/MM.2013.129
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