Issue No.02 - Mar.-Apr. (2014 vol.34)
David Kidd , SuVolta
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2014.8
The Deeply Depleted Channel (DDC) transistor architecture offers 2 to 3 times improvement in body coefficient and 60 percent improvement in local mismatch in 55-nm technology, extending design techniques such as body biasing with voltage scaling to more recent technology nodes. This article presents a body bias architecture for adaptive correction of manufacturing variation, with less than 0.5 percent area penalty for the bias generators. Process monitors with digital readout independently detect p-channel MOS (PMOS) and n-channel MOS (NMOS) process windows. Fujitsu Semiconductor Limited offers DDC technology in its CS250S 55-nm production qualified process, and is currently in production with its first DDC product, a seventh-generation Milbeaut digital-camera processor that performs at twice the performance of the previous generation with 30 percent less power.
Transistors, Threshold voltage, Manufacturing, Logic gates, Random access memory, System-on-chip, Performance evaluation, Program processors, Computer architecture,built-in tests, low-power design
David Kidd, "Process and Circuit Optimization for Power Reduction Using DDC Transistors", IEEE Micro, vol.34, no. 2, pp. 54-62, Mar.-Apr. 2014, doi:10.1109/MM.2014.8