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Issue No.02 - Mar.-Apr. (2014 vol.34)
pp: 34-43
Lucian Codrescu , Qualcomm
Willie Anderson , Qualcomm
Mao Zeng , Qualcomm
Erich Plondke , Qualcomm
Chris Koob , Qualcomm
Ajay Ingle , Qualcomm
Charles Tabony , Qualcomm
Rick Maule , Qualcomm
ABSTRACT
Heterogeneous computing is essential for mobile products to meet power and performance targets. The Qualcomm Hexagon DSP, now in its fifth generation, is used for both modem processing and multimedia acceleration. By offloading multimedia tasks such as voice, audio, sensor, and image processing from the CPU to the DSP, Hexagon achieves significant power savings. Hexagon features a unique architecture that combines application-specific instructions, a VLIW instruction set architecture, and hardware multithreading. The design approach is to maximize work per cycle for performance, but run at modest clock speeds and focus the implementation on low power. This article provides an overview of the Hexagon architecture. The processor is designed to deliver far superior energy efficiency compared to mobile CPU alternatives and thereby help achieve long battery life for important mobile applications.
INDEX TERMS
Program processors, Instruction sets, Digital signal processing, Instruction sets, Multimedia communication, Computer architecture,digital signal processor, Hexagon DSP, multimedia, instruction set architecture
CITATION
Lucian Codrescu, Willie Anderson, Suresh Venkumanhanti, Mao Zeng, Erich Plondke, Chris Koob, Ajay Ingle, Charles Tabony, Rick Maule, "Hexagon DSP: An Architecture Optimized for Mobile Multimedia and Communications", IEEE Micro, vol.34, no. 2, pp. 34-43, Mar.-Apr. 2014, doi:10.1109/MM.2014.12
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