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Fast, Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts
Jan.-Feb. 2014 (vol. 34 no. 1)
pp. 42-53
James Coole, University of Florida
Greg Stitt, University of Florida
High-level synthesis from OpenCL has shown significant potential, but current approaches conflict with mainstream OpenCL design methodologies owing to orders-of-magnitude longer field-programmable gate array compilation times and limited support for changing or adding kernels after system compilation. In this article, the authors introduce a back-end synthesis approach for potentially any OpenCL tool. This approach uses virtual coarse-grained reconfiguration contexts to speed up compilation by 4,211× at a cost of 1.8× system resource overhead, while also enabling 144× faster reconfiguration to support different kernels and rapid changes to kernels.
Index Terms:
Reconfigurable architectures,Context awareness,Field programmable gate arrays,Kernels,Runtime,Finite impulse response filters,intermediate fabrics,OpenCL,FPGA
Citation:
James Coole, Greg Stitt, "Fast, Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts," IEEE Micro, vol. 34, no. 1, pp. 42-53, Jan.-Feb. 2014, doi:10.1109/MM.2013.108
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