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Issue No.06 - Nov.-Dec. (2013 vol.33)
pp: 56-65
Jay Patel , MoSys
Jeff Kumala , MoSys
Ming Liu , MoSys
Memory access rate is a primary performance bottleneck in high-performance networking systems. The MoSys Bandwidth Engine family of integrated circuits provides a significant improvement in effective memory performance by using high-speed serial I/O's, many banks of memory, a low-latency, highly efficient protocol, and intelligence within the device. The first member of the family can perform 2 billion 72-bit reads per second or 1 billion read-modify-write operations per second.
Bandwidth, Memory management, Synchronization, Random access memory, Performance evaluation,semiconductor memories, integrated circuits, interfaces, memory technologies, multiple data stream architectures
Bendik Kleveland, Michael John Miller, Ronald B. David, Jay Patel, Rajesh Chopra, Dipak K. Sikdar, Jeff Kumala, Socrates D. Vamvakos, Mike Morrison, Ming Liu, Jayaprakash Balachandran, "An Intelligent RAM with Serial I/Os", IEEE Micro, vol.33, no. 6, pp. 56-65, Nov.-Dec. 2013, doi:10.1109/MM.2013.7
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