Cool Chips
Nov./Dec. 2013 (Vol. 33, No. 6) pp. 4-5
0272-1732/13/$31.00 © 2013 IEEE

Published by the IEEE Computer Society
Cool Chips
Makoto Ikeda , University of Tokyo

Fumio Arakawa , Nagoya University
  Article Contents  
  The articles  
Download Citation
Download Content
PDFs Require Adobe Acrobat

This introduction to the special section on Cool Chips discusses the state-of-the-art low-power, high-speed chips and challenges facing researchers. It introduces three articles exploring different solutions to reducing power consumption and enhancing chip performance.

Low-power, high-speed chips (Cool Chips) encompass a broad range of architectures, applications, methodologies, and usage models. These technologies are present in multimedia, digital consumer electronics, mobile computing, graphics, encryption, robotics, automobiles, networking, medicine, healthcare, and biometrics. They are based on novel architectures and schemes for single, multi-, and many cores, embedded systems, reconfigurable computing, and dependable computing. Cool software, which includes binary translators and compilers, is also emerging.
These technologies all aim to reduce power consumption and enhance chip performance. Regardless of their goals, all of industry has been challenged with developing optimal solutions—both hardware and software—for power optimization according to the required performance. In general, to migrate decades’ worth of legacy approaches to low-power technology, researchers approach these optimal solutions from the perspective of starting from scratch.
With this in mind, we’ve been organizing annual Cool Chips conferences since 1998. We celebrated Cool Chips XVI in April 2013. Cool Chips, a sister conference to Hot Chips, focuses on all aspects of cool technologies. Approximately 150 individuals attend the conference each year. In addition to regular paper presentations, the conference includes keynote and invited talks, special topic presentations, posters, and panel discussions. To attract submissions from engineers working in industry, the program committee bases acceptance on a short abstract. The conference proceedings include only the short abstract with the final presentation rather than a set of long papers. All program committee members reviewed each of the 21 submissions for Cool Chips XVI and selected the 12 best on the basis of technical merit and innovation.
The articles
This special section of IEEE Micro captures three contributions from among 11 submissions based on the regular and invited papers of Cool Chips XVI. Multicore and many core were major topics at Cool Chips XVI, and the articles we selected for this section reflect this trend.
In “A Scalable 3D Heterogeneous Multicore Processor with an Inductive-Coupling ThruChip Interface,” Noriyuki Miura etal. describe a heterogeneous multicore processor. An inductive-coupling ThruChip Interface (TCI) is applied to its stacked-chip communications, forming a low-cost and robust high-speed 3D Network on Chip (NoC). Processor parallelism can then be widely scaled by simply changing the number of stacked accelerator chips. A prototype system called Cube-1 with 65-nm CMOS test chips achieved successful system operations including 10-hour Linux OS operation. The simulation with clock-level accuracy showed about three times performance acceleration for simple filters and a streaming application in a four-chip stack case.
In “Sparc64 X: Fujitsu’s New-Generation 16-Core Processor for Unix Servers,” Toshio Yoshida etal. describe a processor for Unix servers that runs at a speed of 3 GHz and consists of 16 cores; a 24-Mbyte shared level-2 cache; and memory, I/O, and system controllers for connecting multiple chips. Extremely high-throughput performance is realized by an extended instruction set called HPC-ACE used previously in the K computer and the peak memory bandwidth of 102 Gbytes per second. A new function called software on chip (SWoC) accelerates certain software tasks such as cryptographic processing. A high reliability technology used in mainframes is employed to ensure stable operation of mission-critical systems.
Finally, in “Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor,” Kazuki Fukuoka etal. describe R-Mobile U2, which integrates an application processor and a LTE-capable triple-band baseband processor in 28-nm technology to provide rich content to the midrange smartphone market. Several power-management techniques are equipped in it, including low-leakage power switch, dual-standby-mode static RAM, and frequency control for maximum power suppression.
Low power, low energy, power and energy efficiency, and power and energy awareness are still some of the most important factors for any kind of chip design. To cope with this subject, not only devices and circuits but also a wide variety of innovations—including architecture, algorithms, and software—are essential. The Cool Chips conference series will continue to cover all kinds of low-power and high-performance chips, and we are looking for future contributions. For more information or to submit an abstract, visit
It has been a pleasure to put together this special section on Cool Chips. We thank Editor in Chief Erik Altman for his support and guidance. We also thank Tadao Nakamura, advisory committee chair of Cool Chips 2013, and Hiroaki Kobayashi, organizing committee chair, for their help in arranging this special section. The Cool Chips special section would not have been possible without their help.
Makoto Ikeda is a professor in Department of Electrical Engineering and Information Systems at the University of Tokyo. His research interests include high-performance, low-power, and reliable digital circuit and smart image sensor design. Ikeda has a PhD in electronic engineering from the University of Tokyo. He is a member of IEEE, the ACM, the Institute of Electronics, Information and Communication Engineers (IEICE), and the Information Processing Society of Japan (IPSJ).
Fumio Arakawa is a designated professor in the Center for Embedded Computing Systems at the Graduate School of Information Science at Nagoya University. His research interests include architecture and microarchitecture of low-power and high-performance microprocessors. Arakawa has a PhD in electrical engineering from the University of Tokyo. He’s a member of IEEE and the Institute of Electronics, Information, and Communication Engineers (IEICE).