Issue No.05 - Sept.-Oct. (2013 vol.33)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2013.90
Because of the breakdown of Dennard scaling, the percentage of a silicon chip that can switch at full frequency drops exponentially with each process generation. This utilization wall forces designers to ensure that, at any point in time, large fractions of their chips are effectively "dark silicon"--that is, significantly underclocked or idle for large periods of time. As exponentially larger fractions of a chip's transistors become dark, silicon area becomes an exponentially cheaper resource relative to power and energy consumption. This shift is driving a new class of architectural techniques that "spend" area to "buy" energy efficiency. All these techniques seek to introduce new forms of heterogeneity into the computational stack. This article begins by examining four promising directions--the "four horsemen"--that have emerged as top contenders for thriving in the dark silicon age. Each direction carries with its virtues deep-seated restrictions that require a careful understanding of the underlying trade-offs and benefits. Furthermore, the author proposes a set of evolutionary dark silicon design principles and examines how one of the "darkest" computing architectures of all, the human brain, trades off energy and area in ways that provide potential insights into more revolutionary directions for computer architecture.
Silicon, Multicore processing, Transistors, Threshold voltage, Electric breakdown, CMOS integrated circuits, Capacitance, Dark silicon, Semiconductor device manufacture, Energy efficiency, Dennard scaling, dark silicon, multicore, utilization wall, four horsemen
"A Landscape of the New Dark Silicon Design Regime", IEEE Micro, vol.33, no. 5, pp. 8-19, Sept.-Oct. 2013, doi:10.1109/MM.2013.90