Issue No.04 - July-Aug. (2013 vol.33)
David J. Palframan , University of Wisconsin-Madison
Nam Sung Kim , University of Wisconsin-Madison
Mikko H. Lipasti , University of Wisconsin-Madison
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2013.72
Resilience to defects and parametric variations is of the utmost concern for future technology generations. Traditional redundancy to repair defects, however, can incur performance penalties owing to multiplexing. This article presents a processor design that incorporates bit-sliced redundancy along the data path. This approach makes it possible to tolerate defects without hurting performance, because the same bit offset is left unused throughout the execution core. In addition, the authors use this approach to enhance performance by avoiding excessively slow critical paths created by random delay variations. Adding a single bit slice, for instance, can reduce the delay overhead of random process variations by 10 percent while providing fault tolerance for 15 percent of the execution core.
Hardware, Path planning, Performance evaluation, Circuit faults, Redundancy, Program processors, Fault tolerance, critical path, fault tolerance, hardware, performance, redundant design, reliability, Spare RIBs, within-die variation
David J. Palframan, Nam Sung Kim, Mikko H. Lipasti, "Resilient High-Performance Processors with Spare RIBs", IEEE Micro, vol.33, no. 4, pp. 26-34, July-Aug. 2013, doi:10.1109/MM.2013.72