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Issue No.04 - July-Aug. (2013 vol.33)
pp: 6-14
Ulya R. Karpuzcu , University of Minnesota
Nam Sung Kim , University of Wisconsin-Madison
Josep Torrellas , University of Illinois at Urbana-Champaign
ABSTRACT
Near-threshold voltage computing (NTC) promises significant improvement in energy efficiency. Unfortunately, when compared to conventional, super-threshold voltage computing (STC), NTC is more sensitive to parametric variation. This results in not only slower and leakier cores, but also substantial speed and power differences between the cores in a many-core chip. NTC's potential cannot be unlocked without addressing the higher impact of variation. To confront variation at the architecture level, the authors introduce a parametric variation model for NTC. They then use the model to show the shortcomings of adapting state-of-the-art STC techniques for variation mitigation to NTC. Finally, they discuss how to tailor variation mitigation to NTC.
INDEX TERMS
Energy efficiency, System-on-chip, Threshold voltage, Random access memory, Delays, Computational modeling, Power distribution, near-threshold voltage, multicores, energy and power efficiency, resilience, parameter variation
CITATION
Ulya R. Karpuzcu, Nam Sung Kim, Josep Torrellas, "Coping with Parametric Variation at Near-Threshold Voltages", IEEE Micro, vol.33, no. 4, pp. 6-14, July-Aug. 2013, doi:10.1109/MM.2013.71
REFERENCES
1. M.B. Taylor, "Is Dark Silicon Useful? Harnessing the Four Horsemen of the Coming Dark Silicon Apocalypse," Proc. 49th ACM/EDAC/IEEE Design Automation Conf., IEEE CS, 2012, pp. 1131-1136.
2. L. Chang et al., "Practical Strategies for Power-Efficient Computing Technologies," Proc. IEEE, Feb. 2010, pp. 215-236.
3. R.G. Dreslinski et al., "Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits," Proc. IEEE, Feb. 2010, pp. 253-266.
4. D. Markovic et al., "Ultralow-Power Design in Near-Threshold Region," Proc. IEEE, Feb. 2010, pp. 237-252.
5. A.A. Sinkar et al., "Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors," IEEE Trans. VLSI Systems, May 2013.
6. S. Jain et al., "A 280mV-to-1.2V Wide-Operating-Range IA-32 Processor in 32 nm CMOS," Proc. IEEE Int'l Solid-State Circuits Conf., IEEE CS, 2012, pp. 66-68.
7. U.R. Karpuzcu et al., "VARIUS-NTV: A Microarchitectural Model to Capture the Increased Sensitivity of Manycores to Process Variations at Near-Threshold Voltages," Proc. 42nd Ann. IEEE/IFIP Int'l Conf. Dependable Systems and Networks, IEEE CS, 2012, pp. 1-11.
8. S. Sarangi et al., "VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects," IEEE Trans. Semiconductor Manufacturing, Feb. 2008, pp. 3-13.
9. L. Chang et al., "An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches," IEEE J. Solid-State Circuits, Apr. 2008, pp. 956-963.
10. G. Chen et al., "Yield-Driven Near-Threshold SRAM Design," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design, IEEE, 2007, pp. 660-666.
11. J.W. Tschanz et al., "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage," IEEE J. Solid-State Circuits, Nov. 2002, pp. 1396-1402.
12. R. Teodorescu and J. Torrellas, "Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors," Proc. 35th Ann. Int'l Symp. Computer Architecture, IEEE, 2008, pp. 363-374.
13. U.R. Karpuzcu et al., "EnergySmart: Toward Energy-Efficient Manycores for Near-Threshold Computing," Proc. IEEE 19th Int'l Symp. High Performance Computer Architecture, IEEE CS, 2013, pp. 542-553.
14. C.-K. Luk et al., "Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation," Proc. ACM SIGPLAN Conf. Programming Language Design and Implementation, ACM, 2005, pp. 190-200.
15. S. Li et al., "McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Many-core Architectures," Proc. 42nd Ann. IEEE/ACM Int'l Symp. Microarchitecture, IEEE CS, 2009, pp. 469-480.
16. C. Bienia et al., The PARSEC Benchmark Suite: Characterization and Architectural Implications, tech. report TR-811-08, Computer Science Dept., Princeton Univ., 2008.
17. X. Sun et al., "Variation Study of the Planar Ground-Plane Bulk MOSFET, SOI FinFET, and Trigate Bulk MOSFET Designs," IEEE Trans. Electron Devices, Oct. 2011, pp. 3294-3299.
18. J. Torrellas, N.S. Kim, and R. Teodorescu, Parameter Variation at Near Threshold Voltage: The Power Efficiency versus Resilience Tradeoff, tech. report, Dept. Computer Science, Univ. Illinois at Urbana-Champaign, 2012; http://iacoma.cs.uiuc.edu/perfecttechnical_report.pdf.
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