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Cache-Conscious Thread Scheduling for Massively Multithreaded Processors
May-June 2013 (vol. 33 no. 3)
pp. 78-85
Timothy G. Rogers, University of British Columbia
Mike O'Connor, AMD Research
Tor M. Aamodt, University of British Columbia
Highly multithreaded architectures introduce another dimension to fine-grained hardware cache management. The order in which the system's threads issue instructions can significantly impact the access stream seen by the caching system. This article studies a set of economically important server applications and presents the cache-conscious wavefront scheduling (CCWS) hardware mechanism, which uses feedback from the memory system to guide the issue-level thread scheduler and shape the access pattern seen by the first-level cache.
Index Terms:
Computer architecture,Multithreading,Hardware,Memory management,Scheduling,Parallel processing,Cache storage,Program processors,parallel processors,cache-conscious wavefront scheduling,GPU,memory systems,thread scheduling,SIMD processors,CCWS,cache,locality
Citation:
Timothy G. Rogers, Mike O'Connor, Tor M. Aamodt, "Cache-Conscious Thread Scheduling for Massively Multithreaded Processors," IEEE Micro, vol. 33, no. 3, pp. 78-85, May-June 2013, doi:10.1109/MM.2013.24
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