The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.02 - March-April (2013 vol.33)
pp: 38-47
ABSTRACT
The zEnterprise EC12 is the latest generation of IBM's System z Enterprise Class mainframe servers. The microprocessor operates at an ultra-high frequency of 5.5 GHz and incorporates many pipeline-optimization and instruction-processing techniques. It also supports innovative instruction- set-architecture extensions for future software exploitation to acquire performance gains. This article highlights the various factors inside the zEC12 microprocessor for achieving the best possible computing performance.
INDEX TERMS
Servers, Instruction sets, Microprocessors, Microprocessor chips, Optimization, Program processors, high-frequency microprocessor, microprocessors, IBM computers, mainframes, zSeries, zEC12, zEnterprise EC12, transactional memory, runtime instrumentation, branch prediction
CITATION
C. Kevin Shum, Fadi Busaba, Christian Jacobi, "IBM zEC12: The Third-Generation High-Frequency Mainframe Microprocessor", IEEE Micro, vol.33, no. 2, pp. 38-47, March-April 2013, doi:10.1109/MM.2013.9
REFERENCES
1. C.K. Shum, "IBM zNext—The 3rd Generation High Frequency Microprocessor Chip," Hot Chips 24, 2012.
2. B.W. Curran et al., "The zEnterprise 196 System and Microprocessor," IEEE Micro, vol. 31, no. 2, 2011, pp. 26-40.
3. B. Greene et al., "High Performance 32nm SOI CMOS with High-k/Metal Gate and 0.149μm2 SRAM and Ultra Low-k Back End with Eleven Levels of Copper," Proc. Symp. VLSI Technology, IEEE Press, 2009, pp. 140-141.
4. N. Butt et al., "A 0.039um2 High Performance eDRAM Cell Based on 32nm High-K/Metal SOI Technology," Proc. IEEE Int'l Electron Devices Meeting, IEEE Press, 2010, pp. 27.5.1-27.5.4.
5. C.F. Webb, "IBM z10: The Next-Generation Mainframe Microprocessor," IEEE Micro, vol. 28, no. 2, 2008, pp. 19-29.
6. J. Bonnano et al., "Two Level Bulk Preload Branch Prediction," to be published in Proc. 19th IEEE Int'l Symp. High Performance Computer Architecture, 2013.
7. M. Herlihy and J.E.B. Moss, "Transactional Memory: Architectural Support for Lock-Free Data Structures," Proc. 20th Ann. Int'l Symp. Computer Architecture (ISCA 93), ACM, 1993, pp. 289-300.
8. R.A. Haring et al., "The IBM Blue Gene/Q Compute Chip," IEEE Micro, vol. 32, no. 2, 2012, pp. 48-60.
9. C.J. Jacobi, T. Slegel, and D. Greiner, "Transactional Memory Architecture and Implementation for IBM System z," IEEE/ACM Symp. Microarchitecture, 2012.
10. T. Yasue et al., "An Efficient Online Path Profiling Framework for Java Just-In-Time Compilers," Proc. 12th Int'l Conf. Parallel Architectures and Compilation Techniques (PACT 03), IEEE CS, 2003, pp. 148-158.
522 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool