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Reducing Transistor Variability for High Performance Low Power Chips
March-April 2013 (vol. 33 no. 2)
pp. 18-26
CMOS integrated-circuit supply-voltage reduction has plateaued in recent years as increased transistor variability has limited transistor-threshold voltage scaling. The deeply depleted channel transistor, implemented on bulk CMOS, provides a low-cost option to re-enable voltage scaling on both future and legacy CMOS fabrication processes by reducing random variability and providing a strong body factor to pull in systematic variation and compensate for environmental effects resulting in 50 percent lower power at matched performance.
Index Terms:
Transistors,CMOS integrated circuits,Voltage control,Random access memory,Threshold voltage,DDC,low power,voltage scaling,VLSI,CMOS,body bias,deeply depleted channel transistor,undoped channel transistor
Citation:
Robert Rogenmoser, Lawrence T. Clark, "Reducing Transistor Variability for High Performance Low Power Chips," IEEE Micro, vol. 33, no. 2, pp. 18-26, March-April 2013, doi:10.1109/MM.2013.10
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