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Centip3De: A 64-Core, 3D Stacked Near-Threshold System
March-April 2013 (vol. 33 no. 2)
pp. 8-16
Ronald G. Dreslinski, University of Michigan
David Fick, University of Michigan
Bharan Giridhar, University of Michigan
Gyouho Kim, University of Michigan
Sangwon Seo, University of Michigan
Matthew Fojtik, University of Michigan
Sudhir Satpathy, University of Michigan
Yoonmyung Lee, University of Michigan
Daeyeon Kim, University of Michigan
Nurrachman Liu, University of Michigan
Michael Wieckowski, University of Michigan
Gregory Chen, University of Michigan
Dennis Sylvester, University of Michigan
David Blaauw, University of Michigan
Trevor Mudge, University of Michigan
Centip3De uses the synergy between 3D integration and near-threshold computing to create a reconfigurable system that provides both energy-efficient operation and techniques to address single-thread performance bottlenecks. The original Centip3De design is a seven-layer 3D stacked design with 128 cores and 256 Mbytes of DRAM. Silicon results show a two-layer, 64-core system in 130-nm technology, which achieved an energy efficiency of 3,930 DMIPS/W.
Index Terms:
Random access memory,Three dimensional displays,Threshold voltage,Integrated circuit interconnections,Through-silicon vias,Power system management,Low power electronics,Centip3De,hardware,integrated circuits,types and design styles,advanced technologies,power management,low-power design
Ronald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory Chen, Dennis Sylvester, David Blaauw, Trevor Mudge, "Centip3De: A 64-Core, 3D Stacked Near-Threshold System," IEEE Micro, vol. 33, no. 2, pp. 8-16, March-April 2013, doi:10.1109/MM.2013.4
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